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參數(shù)資料
| 型號： | EM92603A |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | Dual PLL for 43/46/48/49 MHz Cordless Phone(用于43/46/48/49MHz 25通道頻帶無繩電話的雙鎖相環(huán)) |
| 中文描述： | 雙鎖相環(huán)頻率為43/46/48/49無繩電話（用于43/46/48/49MHz 25通道頻帶無繩電話的雙鎖相環(huán)） |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 123K |
| 代理商： | EM92603A |
3
* This specification are subject to be changed without notice.
Preliminary
EM92602/3A
DUAL PLL FOR 43/46/48/49 MHZ CORDLESS PHONE
4.2.1996
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Sym.
Rating
Value
Unit
V
DD
V
IN
I
IN
, I
OUT
I
DD
, I
SS
T
A
T
STG
DC supply voltage
Input voltage
DC current drain per pin
DC current drain V
DD
or V
SS
pins
Operating temperature range
Storage temperature range
-0.5 to +6.0
-0.5 to V
DD
+0.5
10.0
30.0
-30 to +75
-65 to +150
V
V
mA
mA
°
C
°
C
Symbol
XTALO
Port
O
Function
This output generates reference frequency when it is connected to pin 16 with external
OSC of which frequency is 10.240MHz
Base/Handset changing. Internal pull down.
V
: Base, V
: Handset
The standby pin is uses to save power when no transmit. Internal pull down.
High : transmit and receive active
Low : receive acts only
The signal is derived from the reference oscillator.
This is a N-channel open drain output. External pull-up is needed.
5kHz output (for EM92603A only)
The channel selected pin for LSB. (internal pull down)
The channel selected pin. ( internal pull down)
The channel selected pin. ( internal pull down)
The channel selected pin. ( internal pull down)
The channel selected pin for MSB. ( internal pull down)
The serial input data pin.
Clock input. Each low to high transition of the clock shifts one bit of data into the on-
chip shift register.
Non Connect.
The enable pin controls the data transfer from the shift register to the 5-bit latcch.
A low to high transition latches the data.
Input to programmable divider of TX. AC coupling with VCO.
Minimum input voltage is 200 mVp-p.
Unlock detector output. V
DD
level is unlock.
This is a N-channel open drain output. External pull-down is needed.
Phase detector output for Tx. PDT detects the phase error from Rx PLL and its output
is connected to external low pass filter.
Ground.
Phase detector output for Rx. PDR detects the phase error from Rx PLL and its output
is connected to external low pass filter.
Input of programmable divider for Rx. AC coupling with VCO.
Minimum input voltage is 200 mVp-p.
Power Supply.
To connect crystal (10.240MHz) and capacitor.
MODE
I
/SB
I
5K
O
D0
D1
D2
D3
D4
DI
CLK
I
I
I
I
I
I
I
NC
EN
-
I
TIF
I
/LD
O
PDT
O
V
SS
PDR
-
O
RIF
I
V
DD
XTALI
-
I
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