參數(shù)資料
型號: EN25F40-75VI
廠商: Eon Silicon Solution Inc.
元件分類: FLASH
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 24/33頁
文件大?。?/td> 477K
代理商: EN25F40-75VI
Table 11. 75MHz AC Characteristics
This Data Sheet may be revised by subsequent versions 2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. B, Issue Date: 2007/05/09
EN25F40
(T
a
= 0°C to 70°C or - 40°C to 85°C; V
CC
= 2.7-3.6V)
Symbol
Alt
Serial Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, WRSR
f
R
Serial Clock Frequency for READ, RDSR, RDID
Parameter
Min
D.C.
Typ
Max
Unit
F
R
f
C
75
MHz
D.C.
66
MHz
t
CLH
1
Serial Clock High Time
6
ns
t
CLL
1
Serial Clock Low Time
6
ns
t
CLCH
2
Serial Clock Rise Time (Slew Rate)
0.1
0.1
V / ns
t
CHCL
2
Serial Clock Fall Time (Slew Rate)
V / ns
t
SLCH
t
CSS
CS# Active Setup Time
5
ns
t
CHSH
CS# Active Hold Time
5
ns
t
SHCH
CS# Not Active Setup Time
5
ns
t
CHSL
CS# Not Active Hold Time
5
ns
t
SHSL
t
CSH
CS# High Time
100
ns
t
SHQZ
2
t
DIS
Output Disable Time
6
ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
DVCH
t
DSU
Data In Setup Time
2
ns
t
CHDX
t
DH
Data In Hold Time
5
ns
t
HLCH
HOLD# Low Setup Time ( relative to SCK )
5
ns
t
HHCH
HOLD# High Setup Time ( relative to SCK )
5
ns
t
CHHH
HOLD# Low Hold Time ( relative to SCK )
5
ns
t
CHHL
HOLD# High Hold Time ( relative to SCK )
5
ns
t
HLQZ
2
t
HZ
HOLD# Low to High-Z Output
6
ns
t
HHQZ
2
t
LZ
HOLD# High to Low-Z Output
6
ns
t
CLQV
t
V
Output Valid from SCK
6
ns
t
WHSL
3
Write Protect Setup Time before CS# Low
20
100
ns
t
SHWL
3
Write Protect Hold Time after CS# High
ns
t
DP
2
CS# High to Deep Power-down Mode
3
μs
t
RES1
2
CS# High to Standby Mode without Electronic
Signature read
CS# High to Standby Mode with Electronic
Signature read
Write Status Register Cycle Time
3
μs
t
RES2
2
1.8
μs
t
W
10
15
ms
t
PP
Page Programming Time
1.5
5
ms
t
SE
Sector Erase Time
0.15
0.3
s
t
BE
Block Erase Time
0.8
2
s
t
CE
Note:
1. TS
CKH
+ TS
CKL
must be greater than or equal to 1/
F
CLK
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
Chip
Erase Time
5
10
s
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