參數(shù)資料
型號: EN29LV800AB-70TCP
廠商: Eon Silicon Solution Inc.
英文描述: 8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only
中文描述: 8兆位(1024K × 8位/為512k × 16位)閃存引導(dǎo)扇區(qū)閃存,CMOS 3.0伏,只
文件頁數(shù): 27/41頁
文件大小: 370K
代理商: EN29LV800AB-70TCP
Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
JEDEC
Standard
t
AVAV
t
RC
Read Cycle Time
This Data Sheet may be revised by subsequent versions 2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2005/01/10
EN29LV800A
Speed Options
Description
Test
Setup
-55R
55
-70
70
-90
90
Unit
ns
Min
t
AVQV
t
ACC
Address to Output Delay
CE# = V
IL
OE#
=
V
IL
OE# = V
IL
Max
55
70
90
ns
t
ELQV
t
CE
Chip Enable To Output Delay
Max
55
70
90
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
30
35
ns
t
EHQZ
t
DF
Chip Enable to Output High Z
Max
15
20
20
ns
t
GHQZ
t
DF
Output Enable to Output High Z
Max
15
20
20
ns
t
AXQX
t
OH
Output Hold Time from
Addresses, CE# or OE#,
whichever occurs first
Min
0
0
0
ns
Notes:
For – 55R
For all others:
Vcc = 3.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to Vcc
Timing Measurement Reference Level, Input and Output: 1.5 V
Vcc = 3.0V ± 5%
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 5 ns
Input Pulse Levels: 0.0 V to Vcc
Timing Measurement Reference Level, Input and Output: 1.5 V
Addresses
CE#
OE#
WE#
Outputs
Reset#
RY/BY#
HIGH Z
Output Valid
Addresses Stable
t
ACC
t
DF
t
OH
t
OEH
t
CE
t
OE
t
RC
0V
Figure 5. AC Waveforms for READ Operations
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