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參數(shù)資料
| 型號(hào)： | EP1C6T240I8 |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family |
| 中文描述： | 氣旋FPGA系列 |
| 文件頁(yè)數(shù)： | 9/94頁(yè) |
| 文件大?。?/td> | 1138K |
| 代理商： | EP1C6T240I8 |
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Altera Corporation
9
Preliminary Information
Cyclone FPGA Family Data Sheet
Logic Elements
The smallest unit of logic in the Cyclone architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See
Figure 5
.
Figure 5. Cyclone LE
labclk1
labclk2
labclr2
labpre/aload
Chip-Wide
Carry-In1
Carry-In0
LAB Carry-In
Clock &
Clock Enable
Select
LAB Carry-Out
Carry-Out1
Carry-Out0
Look-Up
Table
(LUT)
Carry
Chain
Row, column,
and direct link
routing
Row, column,
and direct link
routing
Programmable
Register
PRN/ALD
D
CLRN
Q
ENA
Register Bypass
Packed
Register Select
Reset
labclkena1
labclkena2
Synchronous
Load and
Clear Logic
LAB-wide
Synchronous
Load
LAB-wide
Synchronous
Clear
Asynchronous
Clear/Preset/
Load Logic
data1
data2
data4
LUT chain
routing to next LE
labclr1
Local Routing
Register chain
output
ADATA
addnsub
Register
Feedback
Register chain
routing from
previous LE
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