Stratix
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1S10F484C5N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 651/864闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX FPGA 10K LE 484-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Package Height Change 03/March/2008
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 20
绯诲垪锛� Stratix®
LAB/CLB鏁�(sh霉)锛� 1057
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 10570
RAM 浣嶇附瑷堬細 920448
杓稿叆/杓稿嚭鏁�(sh霉)锛� 335
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FBGA锛�23x23锛�
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Altera Corporation
10鈥�1
July 2005
10. Transitioning APEX
Designs to Stratix &
Stratix GX Devices
Introduction
Stratix and Stratix GX devices are Altera鈥檚 next-generation, system-on-
a-programmable-chip (SOPC) solution. Stratix and Stratix GX devices
simplify the block-based design methodology and bridge the gap
between system bandwidth requirements and programmable logic
performance.
This chapter highlights the new features in the Stratix and Stratix GX
devices and provides assistance when transitioning designs from
APEXTM II or APEX 20K devices to the Stratix or Stratix GX architecture.
You should be familiar with the APEX II or APEX 20K architecture and
available device features before using this chapter. Use this chapter in
conjunction with the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet
section of the Stratix GX Device Handbook, Volume 1.
General
Architecture
Stratix and Stratix GX devices offer many new features and architectural
enhancements. Enhanced logic elements (LEs) and the MultiTrackTM
interconnect structure offer reduced resource utilization and
considerable design performance improvement. The MultiTrack
interconnect uses DirectDriveTM technology to ensure the availability of
deterministic routing resources for any design block, regardless of its
placement within the device.
All architectural changes between Stratix and Stratix GX and APEX II or
APEX 20K devices described in this section do not require any design
changes. However, you must resynthesize your design and recompile in
the Quartus II software to target Stratix and Stratix GX devices.
S52012-3.0
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A1010B-1PG84C IC FPGA 1200 GATES 84-CPGA COM
APA600-FGG484A IC FPGA PROASIC+ 600K 484-FBGA
APA600-FG484A IC FPGA PROASIC+ 600K 484-FBGA
EP4CGX150CF23C7 IC CYCLONE IV FPGA 150K 484FBGA
A42MX36-1BG272 IC FPGA MX SGL CHIP 54K 272-PBGA
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EP1S10F484C6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1057 LABs 335 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S10F484C6N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1057 LABs 335 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S10F484C7 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1057 LABs 335 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S10F484C7N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1057 LABs 335 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S10F484I6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1057 LABs 335 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256