
16–10
Altera Corporation
Stratix GX Device Handbook, Volume 2
June 2006
Stratix & Stratix GX I/O Standards
Figure 16–7. SSTL-3 Class I Termination
Figure 16–8. SSTL-3 Class II Termination
SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for
applications such as high-speed DDR SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves
operation in conditions where a bus must be isolated from large stubs.
The SSTL-2 standard specifies an input voltage range of
–0.3 V
≤VI ≤VCCIO + 0.3 V. SSTL-2 requires a 1.25-V VREF and a 1.25-V VTT
to which the series and termination resistors are connected (see
input and output levels.
Figure 16–9. SSTL-2 Class I Termination
Output Buffer
Input Buffer
VTT = 1.5 V
50
Ω
25
Ω
Z = 50
Ω
VREF = 1.5 V
Output Buffer
Input Buffer
VTT = 1.5 V
50
Ω
VTT = 1.5 V
50
Ω
25
Ω
Z = 50
Ω
VREF = 1.5 V
Output Buffer
Input Buffer
VTT = 1.25 V
50
Ω
25
Ω
Z = 50
Ω
VREF = 1.25 V