參數(shù)資料
型號: EP20K100EBI356-2X
廠商: Altera
文件頁數(shù): 26/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 100K 356-BGA
標準包裝: 24
系列: APEX-20K®
LAB/CLB數(shù): 416
邏輯元件/單元數(shù): 4160
RAM 位總計: 53248
輸入/輸出數(shù): 246
門數(shù): 263000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 356-BGA
供應商設(shè)備封裝: 356-BGA(35x35)
16
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Cascade Chain
With the cascade chain, the APEX 20K architecture can implement
functions with a very wide fan-in. Adjacent LUTs can compute portions
of a function in parallel; the cascade chain serially connects the
intermediate values. The cascade chain can use a logical AND or logical OR
(via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each
additional LE provides four more inputs to the effective width of a
function, with a short cascade delay. Cascade chain logic can be created
automatically by the Quartus II software Compiler during design
processing, or manually by the designer during design entry.
Cascade chains longer than ten LEs are implemented automatically by
linking LABs together. For enhanced fitting, a long cascade chain skips
alternate LABs in a MegaLAB structure. A cascade chain longer than one
LAB skips either from an even-numbered LAB to the next even-numbered
LAB, or from an odd-numbered LAB to the next odd-numbered LAB. For
example, the last LE of the first LAB in the upper-left MegaLAB structure
carries to the first LE of the third LAB in the MegaLAB structure. Figure 7
shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in.
Figure 7. APEX 20K Cascade Chain
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4
n – 1)..(4n – 4)]
d[3..0]
d[7..4]
LE
n
LE1
LE2
LE
n
LUT
AND Cascade Chain
OR Cascade Chain
d[(4
n – 1)..(4n – 4)]
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