參數(shù)資料
型號: EP20K100QC208-3V
廠商: Altera
文件頁數(shù): 27/117頁
文件大?。?/td> 0K
描述: IC APEX 20K FPGA 100K 208-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: APEX-20K®
LAB/CLB數(shù): 416
邏輯元件/單元數(shù): 4160
RAM 位總計: 53248
輸入/輸出數(shù): 159
門數(shù): 263000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
Altera Corporation
17
APEX 20K Programmable Logic Device Family Data Sheet
LE Operating Modes
The APEX 20K LE can operate in one of the following three modes:
Normal mode
Arithmetic mode
Counter mode
Each mode uses LE resources differently. In each mode, seven available
inputs to the LE—the four data inputs from the LAB local interconnect,
the feedback from the programmable register, and the carry-in and
cascade-in from the previous LE—are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset, asynchronous load,
synchronous clear, synchronous load, and clock enable control for the
register. These LAB-wide signals are available in all LE modes.
The Quartus II software, in conjunction with parameterized functions
such as LPM and DesignWare functions, automatically chooses the
appropriate mode for common functions such as counters, adders, and
multipliers. If required, the designer can also create special-purpose
functions that specify which LE operating mode to use for optimal
performance. Figure 8 shows the LE operating modes.
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EP20K100QC240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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