參數(shù)資料
型號: EP20K200FC484-3V
廠商: Altera
文件頁數(shù): 55/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 200K 484-BGA
標(biāo)準(zhǔn)包裝: 60
系列: APEX-20K®
LAB/CLB數(shù): 832
邏輯元件/單元數(shù): 8320
RAM 位總計: 106496
輸入/輸出數(shù): 382
門數(shù): 404000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FBGA(23x23)
42
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect. Figure 27 shows how a row IOE connects to the
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Row Interconnect
MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K200FI484-1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP20K200FI484-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K200FI484-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP20K200FI484-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K200FI484-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 832 Macro 382 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256