參數(shù)資料
型號： EP2AGX125EF29I3N
廠商： Altera
文件頁數(shù)： 61/90頁
文件大?。?/td> 0K
描述： IC ARRIA II GX FPGA 125K 780FBGA
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 4
系列： Arria II GX
LAB/CLB數(shù)： 4964
邏輯元件/單元數(shù)： 118143
RAM 位總計： 8315904
輸入/輸出數(shù)： 372
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 780-BBGA
供應商設備封裝： 780-FBGA（29x29）
其它名稱： 544-2705
1–56
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
——
1
ms
fCLBW
PLL closed-loop low bandwidth
—
0.3
—
MHz
PLL closed-loop medium bandwidth
—
1.5
—
MHz
PLL closed-loop high bandwidth (7)
—4
—
MHz
tPLL_PSERR
Accuracy of PLL phase shift
—
±50
ps
tARESET
Minimum pulse width on the areset signal
10
—
ns
tINCCJ (3), (4)
Input clock cycle to cycle jitter (FREF ≥ 100 MHz)
—
0.15
UI (p-p)
Input clock cycle to cycle jitter (FREF < 100 MHz)
—
±750
ps (p-p)
tOUTPJ_DC (5)
Period Jitter for dedicated clock output (FOUT ≥ 100 MHz)
—
175
ps (p-p)
Period Jitter for dedicated clock output (FOUT < 100 MHz)
—
17.5
mUI (p-p)
tOUTCCJ_DC (5)
Cycle to Cycle Jitter for dedicated clock output
(FOUT ≥ 100 MHz)
—
175
ps (p-p)
Cycle to Cycle Jitter for dedicated clock output
(FOUT < 100 MHz)
—
17.5
mUI (p-p)
tOUTPJ_IO (5),
Period Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
600
ps (p-p)
Period Jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
60
mUI (p-p)
tOUTCCJ_IO (5),
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
600
ps (p-p)
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
60
mUI (p-p)
tCASC_OUTPJ_DC
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT ≥100MHz)
—
250
ps (p-p)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT < 100MHz)
—
25
mUI (p-p)
fDRIFT
Frequency drift after PFDENA is disabled for duration of
100 us
—
±10
%
Notes to Table 1–45:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) This specification is limited by the lower of the two: I/O FMAX or FOUT of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 120 ps.
(4) FREF is fIN/N when N = 1.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–64 on page 1–71.
(6) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 Mhz
Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(7) High bandwidth PLL settings are not supported in external feedback mode.
(8) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1–63 on
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
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相關代理商/技術參數(shù)
參數(shù)描述
EP2AGX125EF29I5 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX125EF29I5ES 制造商:Altera Corporation 功能描述:FPGA Arria
EP2AGX125EF29I5N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX125EF29I5NES 制造商:Altera Corporation 功能描述:FPGA Arria 制造商:Altera Corporation 功能描述:FPGA Arria? II GX Family 118143 Cells 500MHz 40nm Technology 0.9V 780-Pin FC-FBGA 制造商:Altera Corporation 功能描述:IC ARRIA II GX FPGA 780FBGA
EP2AGX125EF35C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 452 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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