參數(shù)資料
型號(hào): EP2AGX190FF35I5
廠商: Altera
文件頁數(shù): 79/90頁
文件大?。?/td> 0K
描述: IC ARRIA II GX 190K 1152FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: Arria II GX
LAB/CLB數(shù): 7612
邏輯元件/單元數(shù): 181165
RAM 位總計(jì): 10177536
輸入/輸出數(shù): 612
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1152-BBGA
供應(yīng)商設(shè)備封裝: 1152-FBGA(27x27)
1–72
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
IOE Programmable Delay
Table 1–66 lists the delay associated with each supported IOE programmable delay
chain for Arria II GX devices.
Table 1–67 lists the IOE programmable delay settings for Arria II GZ devices.
Table 1–66. IOE Programmable Delay for Arria II GX Devices
Parameter
Available
Settings
Minimum
Offset
Maximum Offset
Unit
Fast Model
Slow Model
I3
C4
I5
I3
C4
C5
I5
C6
Output
enable pin
delay
7
0
0.413
0.442
0.413
0.814
0.713
0.796
0.801
0.873
ns
Delay from
output
register to
output pin
7
0
0.339
0.362
0.339
0.671
0.585
0.654
0.661
0.722
ns
Input delay
from pin to
internal cell
52
0
1.494
1.607
1.494
2.895
2.520
2.733
2.775
2.944
ns
Input delay
from pin to
input register
52
0
1.493
1.607
1.493
2.896
2.503
2.732
2.774
2.944
ns
DQS bus to
input register
delay
4
0
0.074
0.076
0.074
0.140
0.124
0.147
0.167
ns
Notes to Table 1–66:
(1) The available setting for every delay chain starts with zero and ends with the specified maximum number of settings.
(2) The minimum offset represented in the table does not include intrinsic delay.
Table 1–67. IOE Programmable Delay for Arria II GZ Devices
Parameter
Available
Settings
Minimum
Offset (2)
Maximum Offset
Unit
Fast Model
Slow Model
Industrial
Commercial
C3
I3
C4
I4
D1
15
0
0.462
0.505
0.795
0.801
0.857
0.864
ns
D2
7
0
0.234
0.232
0.372
0.371
0.407
0.405
ns
D3
7
0
1.700
1.769
2.927
2.948
3.157
3.178
ns
D4
15
0
0.508
0.554
0.882
0.889
0.952
0.959
ns
D5
15
0
0.472
0.500
0.799
0.817
0.875
0.882
ns
D6
6
0
0.186
0.195
0.319
0.321
0.345
0.347
ns
Notes to Table 1–67:
(1) You can set this value in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column.
(2) Minimum offset does not include the intrinsic delay.
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參數(shù)描述
EP2AGX190FF35I5N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 7612 LABs 612 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX260EF29C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 10260 LABs 372 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX260EF29C4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 10260 LABs 372 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX260EF29C5 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 10260 LABs 372 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX260EF29C5N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 10260 LABs 372 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256