參數(shù)資料
型號: EP2AGX260FF35C6
廠商: Altera
文件頁數(shù): 16/90頁
文件大?。?/td> 0K
描述: IC ARRIA II GX 260K 1152FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: Arria II GX
LAB/CLB數(shù): 10260
邏輯元件/單元數(shù): 244188
RAM 位總計(jì): 12038144
輸入/輸出數(shù): 612
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1152-BBGA
供應(yīng)商設(shè)備封裝: 1152-FBGA(27x27)
Chapter 1: Device Datasheet for Arria II Devices
1–15
Electrical Characteristics
December 2013
Altera Corporation
I/O Standard Specifications
Table 1–22 through Table 1–35 list input voltage (VIH and VIL), output voltage (VOH
and VOL), and current drive characteristics (IOH and IOL) for various I/O standards
supported by the Arria II device family. They also show the Arria II device family I/O
standard specifications. VOL and VOH values are valid at the corresponding IOH and
IOL, respectively.
1 For an explanation of terms used in Table 1–22 through Table 1–35, refer to “Glossary”
Table 1–22 lists the single-ended I/O standards for Arria II GX devices.
Table 1–23 lists the single-ended I/O standards for Arria II GZ devices.
Table 1–22. Single-Ended I/O Standards for Arria II GX Devices
I/O Standard
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
IOL
(mA)
IOH
(mA)
Min
Typ
Max
Min
Max
Min
Max
Min
3.3 V LVTTL
3.135
3.3
3.465
–0.3
0.8
1.7
3.6
0.45
2.4
4
–4
3.3 V LVCMOS
3.135
3.3
3.465
–0.3
0.8
1.7
3.6
0.2
VCCIO -0.2
2
–2
3.0 V LVTTL
2.85
3
3.15
–0.3
0.8
1.7
VCCIO +
0.3
0.45
2.4
4
–4
3.0 V LVCMOS
2.85
3
3.15
–0.3
0.8
1.7
VCCIO +
0.3
0.2
VCCIO - 0.2
0.1
–0.1
2.5 V LVCMOS
2.375
2.5
2.625
–0.3
0.7
1.7
VCCIO +
0.3
0.4
2
1
–1
1.8 V LVCMOS
1.71
1.8
1.89
–0.3
0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO +
0.3
0.45
VCCIO -
0.45
2–2
1.5 V LVCMOS
1.425
1.5
1.575
–0.3
0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO +
0.3
0.25 ×
VCCIO
0.75 ×
VCCIO
2–2
1.2 V LVCMOS
1.14
1.2
1.26
–0.3
0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO +
0.3
0.25 ×
VCCIO
0.75 ×
VCCIO
2–2
3.0-V PCI
2.85
3
3.15
0.3 ×
VCCIO
0.5 ×
VCCIO
VCCIO +
0.3
0.1 ×
VCCIO
0.9 × VCCIO
1.5
–0.5
3.0-V PCI-X
2.85
3
3.15
0.35 ×
VCCIO
0.5 ×
VCCIO
VCCIO +
0.3
0.1 ×
VCCIO
0.9 × VCCIO
1.5
–0.5
Table 1–23. Single-Ended I/O Standards for Arria II GZ Devices (Part 1 of 2)
I/O Standard
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
IOL
(mA)
IOH
(mA)
Min
Typ
Max
Min
Max
Min
Max
Min
LVTTL
2.85
3
3.15
-0.3
0.8
1.7
3.6
0.4
2.4
2
-2
LVCMOS
2.85
3
3.15
-0.3
0.8
1.7
3.6
0.2
VCCIO - 0.2
0.1
-0.1
2.5 V
2.375
2.5
2.625
-0.3
0.7
1.7
3.6
0.4
2
1
-1
1.8 V
1.71
1.8
1.89
-0.3
0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO +
0.3
0.45
VCCIO -
0.45
2-2
1.5 V
1.425
1.5
1.575
-0.3
0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO +
0.3
0.25 ×
VCCIO
0.75 ×
VCCIO
2-2
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