參數資料
型號: EP2AGX65CU17I5
廠商: Altera
文件頁數: 51/90頁
文件大小: 0K
描述: IC ARRIA II GX FPGA 65K 358UBGA
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 6
系列: Arria II GX
LAB/CLB數: 2530
邏輯元件/單元數: 60214
RAM 位總計: 5371904
輸入/輸出數: 156
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 358-UBGA
供應商設備封裝: 358-UBGA
Chapter 1: Device Datasheet for Arria II Devices
1–47
Switching Characteristics
December 2013
Altera Corporation
Jitter tolerance at 2488.32 Mbps
Jitter frequency = 0.06 KHz
Pattern = PRBS15
> 15
UI
Jitter frequency = 100 KHZ
Pattern = PRBS15
> 1.5
UI
Jitter frequency =
1MHz
Pattern = PRBS15
> 0.15
UI
Jitter frequency = 10 MHz
Pattern = PRBS15
> 0.15
UI
Fibre Channel Transmit Jitter Generation (4), (5)
Total jitter FC-1
Pattern = CRPAT
0.23
0.23
UI
Deterministic jitter FC-1
Pattern = CRPAT
0.11
0.11
UI
Total jitter FC-2
Pattern = CRPAT
0.33
0.33
UI
Deterministic jitter FC-2
Pattern = CRPAT
0.2
0.2
UI
Total jitter FC-4
Pattern = CRPAT
0.52
0.52
UI
Deterministic jitter FC-4
Pattern = CRPAT
0.33
0.33
UI
Fibre Channel Receiver Jitter Tolerance (4), (6)
Deterministic jitter FC-1
Pattern = CJTPAT
> 0.37
UI
Random jitter
FC-1
Pattern = CJTPAT
> 0.31
UI
Sinusoidal jitter FC-1
Fc/25000
> 1.5
UI
Fc/1667
> 0.1
UI
Deterministic jitter FC-2
Pattern = CJTPAT
> 0.33
UI
Random jitter
FC-2
Pattern = CJTPAT
> 0.29
UI
Sinusoidal jitter FC-2
Fc/25000
> 1.5
UI
Fc/1667
> 0.1
UI
Deterministic jitter FC-4
Pattern = CJTPAT
> 0.33
UI
Random jitter FC-4
Pattern = CJTPAT
> 0.29
UI
Sinusoidal jitter FC-4
Fc/25000
> 1.5
UI
Fc/1667
> 0.1
UI
XAUI Transmit Jitter Generation (7)
Total jitter at 3.125 Gbps
Pattern = CJPAT
0.3
0.3
UI
Deterministic jitter at
3.125 Gbps
Pattern = CJPAT
0.17
0.17
UI
XAUI Receiver Jitter Tolerance (7)
Total jitter
> 0.65
UI
Deterministic jitter
> 0.37
UI
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 2 of 7)
Symbol/
Description
Conditions
–C3 and –I3
–C4 and –I4
Unit
Min
Typ
Max
Min
Typ
Max
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