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參數(shù)資料
| 型號： | EP2AGX65CU17I5 |
| 廠商： | Altera |
| 文件頁數(shù)： | 86/90頁 |
| 文件大小： | 0K |
| 描述： | IC ARRIA II GX FPGA 65K 358UBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 6 |
| 系列： | Arria II GX |
| LAB/CLB數(shù)： | 2530 |
| 邏輯元件/單元數(shù)： | 60214 |
| RAM 位總計： | 5371904 |
| 輸入/輸出數(shù)： | 156 |
| 電源電壓： | 0.87 V ~ 0.93 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 358-UBGA |
| 供應(yīng)商設(shè)備封裝： | 358-UBGA |
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December 2010
AIIGX53002-2.0
2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
2. Addendum for the Arria II Device
Handbook
This chapter describes changes to the published version of the Arria II Device
Handbook. All changes from Revision 1.1 of this chapter are now incorporated in the
main handbook chapters.
Highlights
f This information is now located in the Overview for the Arria II Device Family chapter.
High-Speed LVDS I/O with DPA and Soft CDR
f This information is now located in the Overview for the Arria II Device Family chapter.
Auto-Calibrating External Memory Interfaces
f This information is now located in the Overview for the Arria II Device Family chapter.
Connecting a Serial Configuration Device to an Arria II Device Family
on AS Interface
f This information is now located in the Configuration, Design Security, and Remote
Document Revision History
Table 2–1 lists the revision history for this chapter.
Table 2–1. Document Revision History
Date
Version
Changes
December 2010
2.0
■ Updated chapter titles.
July 2010
1.2
■ Moved the “Highlights”, “High-Speed LVDS I/O with DPA and Soft CDR”, and
“Auto-Calibrating External Memory Interfaces” sections to the
Arria II GX Device Family Overview chapter.
■ Moved the “Guidelines for Connecting Serial Configuration Device to Arria II GX
Device Family on AS Interface” section to the Configuration, Design Security, and
Remote System Upgrades in Arria II GX Devices chapter
March 2010
1.1
Added “Guidelines for Connecting Serial Configuration Device to Arria II GX Device
Family on AS Interface”
February 2010
1.0
Initial release.
December 2010
AIIGX53002-2.0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2AGX65CU17I5N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 2530 LABs 156 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2AGX65CU17I5NAA | 制造商:Altera Corporation 功能描述:FPGA Arria |
| EP2AGX65DF25C4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2AGX65DF25C4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2AGX65DF25C5 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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