參數(shù)資料
型號(hào): EP2AGX95EF29I5N
廠商: Altera
文件頁數(shù): 20/90頁
文件大?。?/td> 0K
描述: IC ARRIA II GX FPGA 95K 780FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 4
系列: Arria II GX
LAB/CLB數(shù): 3747
邏輯元件/單元數(shù): 89178
RAM 位總計(jì): 6839296
輸入/輸出數(shù): 372
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 780-BBGA
供應(yīng)商設(shè)備封裝: 780-FBGA(29x29)
Chapter 1: Device Datasheet for Arria II Devices
1–19
Electrical Characteristics
December 2013
Altera Corporation
Table 1–30 lists the HSTL I/O standards for Arria II GX devices.
Table 1–31 lists the HSTL I/O standards for Arria II GZ devices.
Table 1–32 lists the differential I/O standard specifications for Arria II GX devices.
Table 1–30. Differential HSTL I/O Standards for Arria II GX Devices
I/O Standard
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
HSTL-18 Class I
1.71
1.8
1.89
0.2
0.85
0.95
0.88
0.95
0.4
HSTL-15 Class I, II
1.425
1.5
1.575
0.2
0.71
0.79
0.71
0.79
0.4
HSTL-12 Class I, II
1.14
1.2
1.26
0.16
0.5 ×
VCCIO
0.48
×
VCCIO
0.5 ×
VCCIO
0.52 ×
VCCIO
0.3
Table 1–31. Differential HSTL I/O Standards for Arria II GZ Devices
I/O Standard
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
HSTL-18 Class I
1.71
1.8
1.89
0.2
0.78
1.12
0.78
1.12
0.4
HSTL-15 Class I, II
1.425
1.5
1.575
0.2
0.68
0.9
0.68
0.9
0.4
HSTL-12 Class I, II
1.14
1.2
1.26
0.16
VCCIO
+ 0.3
0.5 ×
VCCIO
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
0.3
VCCIO
+
0.48
Table 1–32. Differential I/O Standard Specifications for Arria II GX Devices (Note 1)
I/O
Standard
VCCIO (V)
VID (mV)
VICM (V) (2)
VOD (V) (3)
VOCM (V)
Min
Typ
Max
Min
Cond.
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
2.5 V
LVDS
2.375
2.5
2.625
100
VCM =
1.25 V
0.05
1.80
0.247
0.6
1.125
1.25
1.375
RSDS (4)
2.375
2.5
2.625
0.1
0.2
0.6
0.5
1.2
1.4
Mini-LVDS
2.375
2.5
2.625
0.25
0.6
1
1.2
1.4
LVPECL
2.375
2.5
2.625
300
0.6
1.8
2.375
2.5
2.625
100
Notes to Table 1–32:
(1) The 1.5 V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 1–21.
(2) VIN range: 0 <= VIN <= 1.85 V.
(3) RL range: 90 <= RL <= 110 .
(4) The RSDS and mini-LVDS I/O standards are only supported for differential outputs.
(5) The LVPECL input standard is supported at the dedicated clock input pins (GCLK) only.
(6) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. These specifications depend on the system topology.
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