參數(shù)資料
型號: EP2AGX95EF29I5N
廠商: Altera
文件頁數(shù): 66/90頁
文件大?。?/td> 0K
描述: IC ARRIA II GX FPGA 95K 780FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 4
系列: Arria II GX
LAB/CLB數(shù): 3747
邏輯元件/單元數(shù): 89178
RAM 位總計: 6839296
輸入/輸出數(shù): 372
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 780-BBGA
供應(yīng)商設(shè)備封裝: 780-FBGA(29x29)
Chapter 1: Device Datasheet for Arria II Devices
1–61
Switching Characteristics
December 2013
Altera Corporation
Periphery Performance
This section describes periphery performance, including high-speed I/O, external
memory interface, and IOE programmable delay.
I/O performance supports several system interfaces, for example the high-speed I/O
interface, external memory interface, and the PCI/PCI-X bus interface. I/O using
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speed with typical DDR2 SDRAM memory interface setup. I/O using
general purpose I/O (GPIO) standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS
are capable of typical 200 MHz interfacing frequency with 10pF load.
1 Actual achievable frequency depends on design- and system-specific factors. You
should perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 1–53 lists the high-speed I/O timing for Arria II GX devices.
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 1 of 4)
Symbol
Conditions
I3
C4
C5,I5
C6
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Clock
fHSCLK_IN
(input clock
frequency)–Row
I/O
Clock boost
factor, W =
1 to 40 (1)
5
670
5
670
5
622
5
500
MHz
fHSCLK_IN
(input clock
frequency)–
Column I/O
Clock boost
factor, W =
1 to 40 (1)
5
500
5
500
5
472.5
5
472.5
MHz
fHSCLK_OUT
(output clock
frequency)–Row
I/O
5
670
5
670
5
622
5
500
MHz
fHSCLK_OUT
(output clock
frequency)–
Column I/O
5
500
5
500
5
472.5
5
472.5
MHz
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