參數(shù)資料
型號: EP4CE22F17I8LN
廠商: Altera
文件頁數(shù): 6/42頁
文件大小: 0K
描述: IC CYCLONE IV E FPGA 22K 256FBGA
產(chǎn)品培訓(xùn)模塊: Designing an IP Surveillance Camera
Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品: Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝: 90
系列: CYCLONE® IV E
LAB/CLB數(shù): 1395
邏輯元件/單元數(shù): 22320
RAM 位總計: 608256
輸入/輸出數(shù): 153
電源電壓: 0.97 V ~ 1.03 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FBGA(17x17)
其它名稱: 544-2657
1–14
Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
December 2013
Altera Corporation
f For more information about receiver input and transmitter output waveforms, and for
other differential I/O standards, refer to the I/O Features in Cyclone IV Devices chapter.
Table 1–18. Differential SSTL I/O Standard Specifications for Cyclone IV Devices (1)
I/O Standard
VCCIO (V)
VSwing(DC) (V)
VX(AC) (V)
VSwing(AC)
(V)
VOX(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Max
Min
Typ
Max
SSTL
-2
Class I, II
2.375
2.5
2.625 0.36
VCCIO VCCIO/2 – 0.2
VCCIO/2
+ 0.2
0.7
VCCI
O
VCCIO/2 –
0.125
VCCIO/2
+ 0.125
SSTL
-18
Class I, II
1.7
1.8
1.90
0.25
VCCIO
VCCIO/2 –
0.175
VCCIO/2
+ 0.175
0.5
VCCI
O
VCCIO/2 –
0.125
VCCIO/2
+ 0.125
Note to Table 1–18:
(1) Differential SSTL requires a VREF input.
Table 1–19. Differential HSTL I/O Standard Specifications for Cyclone IV Devices (1)
I/O Standard
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Mi
n
Max
HSTL
-18
Class I, II
1.71
1.8
1.89
0.2
0.85
0.95
0.85
0.95
0.4
HSTL
-15
Class I, II
1.425
1.5
1.575
0.2
0.71
0.79
0.71
0.79
0.4
HSTL
-12
Class I, II
1.14
1.2
1.26
0.16
VCCIO
0.48 x VCCIO
0.52 x
VCCIO
0.48 x
VCCIO
0.52 x
VCCIO
0.3
0.48 x
VCCIO
Note to Table 1–19:
(1) Differential HSTL requires a VREF input.
Table 1–20. Differential I/O Standard Specifications for Cyclone IV Devices (1) (Part 1 of 2)
I/O Standard
VCCIO (V)
VID (mV)
VIcM (V) (2)
VOD (mV) (3)
VOS (V) (3)
Min
Typ
Max
Min
Max
Min
Condition
Max
Min
Typ
Max
Min
Typ
Max
LVPECL
(Row I/Os)
2.375
2.5
2.625
100
0.05
DMAX500 Mbps
1.80
———
0.55
500 Mbps
D
MAX
700 Mbps
1.80
1.05
DMAX > 700 Mbps
1.55
LVPECL
(Column
I/Os) (6)
2.375
2.5
2.625
100
0.05
DMAX 500 Mbps
1.80
———
0.55
500 Mbps
D
MAX
700 Mbps
1.80
1.05
DMAX > 700 Mbps
1.55
LVDS (Row
I/Os)
2.375
2.5
2.625
100
0.05
DMAX 500 Mbps
1.80
247
600
1.125
1.25
1.375
0.55
500 Mbps
D
MAX
700 Mbps
1.80
1.05
DMAX > 700 Mbps
1.55
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