參數(shù)資料
型號(hào)： EP4S100G2F40I1N
廠商： Altera
文件頁數(shù)： 16/22頁
文件大小： 0K
描述： IC STRATIX IV FPGA 230K 1517FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 3
系列： STRATIX® IV GT
LAB/CLB數(shù)： 9120
邏輯元件/單元數(shù)： 228000
RAM 位總計(jì)： 17544192
輸入/輸出數(shù)： 654
電源電壓： 0.92 V ~ 0.98 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1517-BBGA
供應(yīng)商設(shè)備封裝： 1517-FBGA（40x40）
Chapter 1: Overview for the Stratix IV Device Family
1–3
Feature Summary
September 2012
Altera Corporation
Stratix IV GX Devices
Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels
per device:
■
Thirty-two out of the 48 transceiver channels have dedicated physical coding
sublayer (PCS) and physical medium attachment (PMA) circuitry and support
data rates between 600 Mbps and 8.5 Gbps
■
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
1 The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to Table 1–1
1 For more information about transceiver architecture, refer to the Transceiver
Figure 1–1 shows a high-level Stratix IV GX chip view.
Figure 1–1. Stratix IV GX Chip View (1)
(1) Resource counts vary with device selection, package selection, or both.
General Purpose
I/O and Memory
Interface
600 Mbps-8.5 Gbps CDR-based Transceiver
General Purpose I/O and 150 Mbps-1.6 Gbps
LVDS interface with DPA and Soft-CDR
T
ransceiv
er
Bloc
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T
ransceiv
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Bloc
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PCI
Express
Hard
IP
Bloc
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PCI
Express
Hard
IP
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PCI
Express
Hard
IP
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PCI
Express
Hard
IP
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General Purpose
I/O and Memory
Interface
PLL
General Purpose
I/O and Memory
Interface
General Purpose
I/O and Memory
Interface
PLL
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
Transceiver Block
General Purpose I/O and
High-Speed LVDS I/O
with DPA and Soft CDR
Gener
al
Pur
pose
I/O
and
High-Speed
LVDS
I/O
with
DP
A
and
Soft
CDR
PLL
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Bloc
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T
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er
Bloc
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T
ransceiv
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Bloc
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T
ransceiv
er
Bloc
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Gener
al
Pur
pose
I/O
and
High-Speed
LVDS
I/O
with
DP
A
and
Soft
CDR
Gener
al
Pur
pose
I/O
and
High-Speed
LVDS
I/O
with
DP
A
and
Soft
CDR
Gener
al
Pur
pose
I/O
and
High-Speed
LVDS
I/O
with
DP
A
and
Soft
CDR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP4S100G2F40I2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4S100G2F40I2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4S100G3F45I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4S100G3F45I1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4S100G3F45I2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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