參數(shù)資料
| 型號： | EP4S100G2F40I1N |
| 廠商： | Altera |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX IV FPGA 230K 1517FBGA |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB數(shù)： | 9120 |
| 邏輯元件/單元數(shù)： | 228000 |
| RAM 位總計： | 17544192 |
| 輸入/輸出數(shù)： | 654 |
| 電源電壓： | 0.92 V ~ 0.98 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1517-BBGA |
| 供應商設備封裝： | 1517-FBGA（40x40） |
1–16
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
September 2012
Altera Corporation
Table 1–5 summarizes the Stratix IV E device package options.
Table 1–6 lists the Stratix IV E on-package decoupling information.
Table 1–7 lists the Stratix IV GT device features.
Device
F780
F1152
(35 mm x 35 mm) (5), (7)
F1517
(40 mm x 40 mm) (7)
F1760
(42.5 mm x 42.5 mm) (7)
EP4SE230
F29
—
EP4SE360
H29 (3)
F35
—
EP4SE530
—
H35 (4)
H40 (4)
F43
EP4SE820
—
H35 (4)
H40 (4)
F43
Notes to Table 1–5:
(1) Device packages in the same column and marked under the same arrow sign have vertical migration capability.
(2) Use the Pin Migration Viewer in the Pin Planner to verify the pin migration compatibility when migrating devices. For more information, refer to
I/O Management in the Quartus II Handbook, Volume 2.
(3) The 780-pin EP4SE360 device is available only in the 33 mm x 33 mm Hybrid flip chip package.
(4) The 1152-pin and 1517-pin for EP4SE530 and EP4SE820 devices are available only in the 42.5 mm x 42.5 mm Hybrid flip chip package.
(5) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information, refer to the Package
(6) Devices listed in this column do not have on-package decoupling capacitors.
(7) Devices listed in this column have on-package decoupling capacitors. For more information about on-package decoupling capacitor value for
each device, refer to Table 1–6.
Table 1–6. Stratix IV E Device On-Package Decoupling Information (1)
Ordering Information
VCC
VCCIO
EP4SE360
F35
4
1 uF + 4470 nF
10 nF per bank
EP4SE530
H35
H40
F43
4
1 uF + 4470 nF
10 nF per bank
EP4SE820
H35
H40
F43
4
1 uF + 4470 nF
10 nF per bank
Note to Table 1–6:
(1) Table 1–6 refers to production devices on-package decoupling. For more information about decoupling design of engineering sample (ES)
devices, contact Altera Technical Support.
Table 1–7. Stratix IV GT Device Features (Part 1 of 2)
Feature
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
Package Pin Count
1517
1932
1517
1932
ALMs
91,200
212,480
91,200
116,480
141,440
212,480
LEs
228,000
531,200
228,000
291,200
353,600
531,200
Total Transceiver
Channels
36
48
36
48
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP4S100G2F40I2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G2F40I2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G3F45I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G3F45I1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G3F45I2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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