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參數(shù)資料
| 型號： | EP4S100G5H40I2N |
| 廠商： | Altera |
| 文件頁數(shù)： | 61/82頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV GT 530K 1517HBGA |
| 產品培訓模塊： | Stratix IV FPGAs Three Reasons to Use FPGA's in Industrial Designs |
| 特色產品： | Stratix? IV Series FPGAs |
| 標準包裝： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB數(shù)： | 21248 |
| 邏輯元件/單元數(shù)： | 531200 |
| RAM 位總計： | 28033024 |
| 輸入/輸出數(shù)： | 654 |
| 電源電壓： | 0.92 V ~ 0.98 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1517-BBGA 裸露焊盤 |
| 供應商設備封裝： | 1517-HBGA（42.5x42.5） |
| 其它名稱： | 544-2636 |
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
TCCS
True Differential I/O Standards
—
100
—
100
—
100
ps
Emulated Differential I/o
Standards
—
250
—
250
—
250
ps
Receiver
True Differential I/O
Standards -
fHSDRDPA (data rate)
SERDES factor J = 3 to 10 (11)
150
—
1600
150
—
1250
150
—
1250
Mbps
fHSDR (data rate)
SERDES factor J = 3 to 10
—
—
—
Mbps
SERDES factor J = 2,
Uses DDR Registers
—
—
—
Mbps
SERDES factor J = 1,
Uses an SDR Register
—
—
—
Mbps
DPA Mode
DPA run length
—
10000
—
10000
—
10000
UI
Soft CDR mode
Soft-CDR PPM
tolerance
—
300
—
300
—
300
±
PPM
Non DPA Mode
Sampling Window
—
300
—
300
—
300
ps
Notes to Table 1–42:
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) For 820, 530, 360, and 290 density devices, the frequency is 762 MHz.
(5) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local)
that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(6) The maximum ideal frequency is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the
signal integrity simulation is clean.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(8) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew
margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(9) This is achieved by using the LVDS and DPA clock network.
(10) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(11) The fMAX specification is based on the fast clock used for serial data. The interface fMAX also depends on the parallel clock domain, which is design
dependent and requires timing analysis.
(12) This only applies to DPA and soft-CDR modes.
(13) This only applies to LVDS source synchronous mode.
Table 1–42. High-Speed I/O Specifications (1), (2) (Part 3 of 3)
Symbol
Conditions
–2/–2× Speed Grade
–3 Speed Grade
–4 Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP4S100G5H40I3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G5H40I3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40C2NES1 | 制造商:Altera Corporation 功能描述:IC STRATIX IV GT FPGA 1517FBGA |
| EP4S40G2F40I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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