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參數(shù)資料
| 型號： | EP4S100G5H40I3N |
| 廠商： | Altera |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX IV FPGA 530K 1517HBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB數(shù)： | 21248 |
| 邏輯元件/單元數(shù)： | 531200 |
| RAM 位總計： | 28033024 |
| 輸入/輸出數(shù)： | 654 |
| 電源電壓： | 0.92 V ~ 0.98 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1517-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 1517-HBGA（42.5x42.5） |
1–18
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
September 2012
Altera Corporation
Table 1–8 lists the resource counts for the Stratix IV GT devices.
Table 1–9 lists the Stratix IV GT on-package decoupling information.
Table 1–8. Stratix IV GT Device Package Options (1), (2)
Device
1517 Pin
(40 mm x 40 mm) (3)
1932 Pin
(45 mm x 45 mm)
Stratix IV GT 40 G Devices
EP4S40G2
F40
—
EP4S40G5
H40 (4), (5)
—
Stratix IV GT 100 G Devices
EP4S100G2
F40
—
EP4S100G3
—
F45
EP4S100G4
—
F45
EP4S100G5
H40 (4), (5)
F45
Notes to Table 1–8:
(1) This table represents pin compatability; however, it does not include hard IP block placement compatability.
(2) Devices under the same arrow sign have vertical migration capability.
(3) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information,
refer to the Altera Device Package Information Data Sheet.
(4) EP4S40G5 and EP4S100G5 devices with 1517 pin-count are only available in 42.5-mm x 42.5-mm Hybrid flip chip
packages.
(5) If you are using the hard IP block, migration is not possible.
Table 1–9. Stratix IV GT Device On-Package Decoupling Information (1)
Ordering
Information
VCC
VCCIO
VCCL_GXB
VCCA_L/R
VCCT_L/R
VCCR_L/R
EP4S40G2F40
EP4S100G2F40
2
1 uF + 2470 nF 10 nF per bank (2)
100 nF per
transceiver block
100 nF
EP4S100G3F45
4
1 uF + 4470 nF 10 nF per bank (2)
100 nF per
transceiver block
100 nF
EP4S100G4F45
EP4S40G5H40
EP4S100G5H40
EP4S100G5F45
Notes to Table 1–9:
(1) Table 1–9 refers to production devices on-package decoupling. For more information about decoupling design of engineering sample (ES)
devices, contact Altera Technical Support.
(2) For I/O banks 3(*), 4(*), 7(*), and 8(*) only. There is no OPD for I/O bank 1(*), 2(*), 5(*), and 6(*).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP4S40G2F40C2NES1 | 制造商:Altera Corporation 功能描述:IC STRATIX IV GT FPGA 1517FBGA |
| EP4S40G2F40I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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