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參數(shù)資料
| 型號： | EP4S100G5H40I3N |
| 廠商： | Altera |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX IV FPGA 530K 1517HBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB數(shù)： | 21248 |
| 邏輯元件/單元數(shù)： | 531200 |
| RAM 位總計： | 28033024 |
| 輸入/輸出數(shù)： | 654 |
| 電源電壓： | 0.92 V ~ 0.98 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1517-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 1517-HBGA（42.5x42.5） |
1–2
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
September 2012
Altera Corporation
Feature Summary
The following list summarizes the Stratix IV device family features:
■
Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices
supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively
■
Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE),
Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre
Channel, SFI-5, and Interlaken
■
Complete PCIe protocol solution with embedded PCIe hard IP blocks that
implement PHY-MAC layer, Data Link layer, and Transaction layer functionality
f For more information, refer to the IP Compiler for PCI Express User Guide.
■
Programmable transmitter pre-emphasis and receiver equalization circuitry to
compensate for frequency-dependent losses in the physical medium
■
Typical physical medium attachment (PMA) power consumption of 100 mW at
3.125 Gbps and 135 mW at 6.375 Gbps per channel
■
72,600 to 813,050 equivalent LEs per device
■
7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block
sizes to implement true dual-port memory and FIFO buffers
■
High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit,
12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz
■
Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery
clocks (PCLK) per device
■
Programmable power technology that minimizes power while maximizing device
performance
■
Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide
range of single-ended and differential I/O standards
■
Support for high-speed external memory interfaces including DDR, DDR2,
DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular
I/O banks
■
High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic
phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps
■
Support for source-synchronous bus standards, including SGMII, GbE, SPI-4
Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
■
Pinouts for Stratix IV E devices designed to allow migration of designs from
Stratix III to Stratix IV E with minimal PCB impact
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP4S40G2F40C2NES1 | 制造商:Altera Corporation 功能描述:IC STRATIX IV GT FPGA 1517FBGA |
| EP4S40G2F40I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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