參數資料
型號: EP4SE360H29I4N
廠商: Altera
文件頁數: 41/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV FPGA 360K 780HBGA
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 3
系列: STRATIX® IV E
LAB/CLB數: 14144
邏輯元件/單元數: 353600
RAM 位總計: 23105536
輸入/輸出數: 488
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 780-BBGA 裸露焊盤
供應商設備封裝: 780-HBGA(33x33)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–38
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Total jitter at 5 Gbps
(Gen2)
Compliance pattern
Compliant
UI
PCIe (Gen 1) Electrical Idle Detect Threshold
VRX-IDLE-DETDIFFp-p (16)
Compliance pattern
65
175
65
175
65
175
UI
Serial RapidIO Transmit Jitter Generation (8)
Deterministic jitter
(peak-to-peak)
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
0.17
0.17
0.17
UI
Total jitter
(peak-to-peak)
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
0.35
0.35
0.35
UI
Serial RapidIO Receiver Jitter Tolerance (8)
Deterministic jitter
tolerance (peak-to-peak)
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
> 0.37
UI
Combined deterministic
and random jitter
tolerance (peak-to-peak)
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
> 0.55
UI
Sinusoidal jitter
tolerance (peak-to-peak)
Jitter Frequency = 22.1
KHz Data Rate = 1.25,
2.5, 3.125 Gbps
Pattern = CJPAT
> 8.5
UI
Jitter Frequency = 1.875
MHz
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
> 0.1
UI
Jitter Frequency =
20 MHz
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
> 0.1
UI
GIGE Transmit Jitter Generation (9)
Deterministic jitter
(peak-to-peak)
Pattern = CRPAT
0.14
0.14
0.14
UI
Total jitter
(peak-to-peak)
Pattern = CRPAT
0.279
0.279
0.279
UI
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1), (2) (Part 3 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
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