參數(shù)資料
| 型號： | EP4SGX110HF35C4 |
| 廠商： | Altera |
| 文件頁數(shù)： | 77/82頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 110K 1152FBGA |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | Stratix® IV GX |
| LAB/CLB數(shù)： | 4224 |
| 邏輯元件/單元數(shù)： | 105600 |
| RAM 位總計： | 9793536 |
| 輸入/輸出數(shù)： | 488 |
| 電源電壓： | 0.87 V ~ 0.93 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1152-BBGA |
| 供應商設備封裝： | 1152-FBGA（27x27） |
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SIV54002-1.5
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
February 2011
2. Addendum to the Stratix IV Device
Handbook
This chapter describes changes to the published version of the Stratix IV Device
Handbook. All changes from Revision 1.4 of this chapter are now incorporated in the
main handbook chapters or in AN 612: Decision Feedback Equalization in Stratix IV
Adaptive Equalization (AEQ)
f This AEQ information is now located in the Dynamic Reconfiguration in Stratix IV
Devices chapter.
Decision Feedback Equalization (DFE)
f For more information about the DFE feature, refer to AN 612: Decision Feedback
Power-On Reset Circuitry
The Power-On Reset Circuitry information is now located in the Hot Socketing and
Power-On Reset in Stratix IV Devices chapter.
Power-On Reset Specifications
f The Power-On Reset Specification information is now located in the Hot Socketing and
Power-On Reset in Stratix IV Devices chapter.
February 2011
SIV54002-1.5
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP4SGX110HF35C4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 4224 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX110HF35I3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 4224 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX110HF35I3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 4224 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX110HF35I4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 4224 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX110HF35I4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 4224 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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