參數(shù)資料
型號(hào)： EP4SGX180KF40I4N
廠商： Altera
文件頁(yè)數(shù)： 53/82頁(yè)
文件大小： 0K
描述： IC STRATIX IV FPGA 180K 1517FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 3
系列： Stratix® IV GX
LAB/CLB數(shù)： 7030
邏輯元件/單元數(shù)： 175750
RAM 位總計(jì)： 13954048
輸入/輸出數(shù)： 744
電源電壓： 0.87 V ~ 0.93 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1517-BBGA
供應(yīng)商設(shè)備封裝： 1517-FBGA（40x40）
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–49
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
tOUTCCJ_DC (6)
Cycle to Cycle Jitter for dedicated clock output
(FOUT ≥ 100 MHz)
—
175
ps (p-p)
Cycle to Cycle Jitter for dedicated clock output
(FOUT < 100 MHz)
—
17.5
mUI (p-p)
tOUTPJ_IO (6),
Period Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
600
ps (p-p)
Period Jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
60
mUI (p-p)
tOUTCCJ_IO (6),
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
600
ps (p-p)
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
60
mUI (p-p)
tCASC_OUTPJ_DC
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT ≥100MHz)
—
250
ps (p-p)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT < 100MHz)
—
25
mUI (p-p)
fDRIFT
Frequency drift after PFDENA is disabled for duration of
100 us
—
±10
%
Notes to Table 1–34:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(3) This specification is limited by the lower of the two: I/O FMAX or FOUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 120 ps.
(5) FREF is fIN/N when N = 1.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–51 on page 1–62.
(7) The cascaded PLL specification is only applicable with the following condition:
A. Upstream PLL: 0.59Mhz
Upstream PLL BW < 1 MHz
B. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1–49 on
Table 1–34. PLL Specifications for Stratix IV Devices (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP4SGX230 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:Stratix IV Device
EP4SGX230DF29C2NES 制造商:Altera Corporation 功能描述:IC FPGA 372 I/O 780FBGA 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 780FBGA
EP4SGX230DF29C2X 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 9120 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX230DF29C2XES 制造商:Altera Corporation 功能描述:IC FPGA 372 I/O 780FBGA 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 780FBGA
EP4SGX230DF29C2XN 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 9120 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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