參數(shù)資料
型號(hào)： EP4SGX530KH40C2
廠商： Altera
文件頁(yè)數(shù)： 66/82頁(yè)
文件大小： 0K
描述： IC STRATIX IV FPGA 530K 1517HBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 3
系列： Stratix® IV GX
LAB/CLB數(shù)： 21248
邏輯元件/單元數(shù)： 531200
RAM 位總計(jì)： 28033024
輸入/輸出數(shù)： 744
電源電壓： 0.87 V ~ 0.93 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 1517-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 1517-HBGA（42.5x42.5）
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–61
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Table 1–49 lists the memory output clock jitter specifications for Stratix IV devices.
OCT Calibration Block Specifications
Table 1–50 lists the OCT calibration block specifications for Stratix IV devices.
Table 1–49. Memory Output Clock Jitter Specification for Stratix IV Devices (1), (2), (3), (4)
Parameter
Clock
Network
Symbol
–2/–2X
Speed Grade
–3
Speed Grade
–4
Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Clock period jitter
Regional
t
JIT(per)
-5050-55
55-5555
ps
Cycle-to-cycle period jitter
Regional
t
JIT(cc)
-100
100
-110
110
-110
110
ps
Duty cycle jitter
Regional
t
JIT(duty)
-50
50
-82.5
82.5
-82.5
82.5
ps
Clock period jitter
Global
t
JIT(per)
-75
75
-82.5
82.5
-82.5
82.5
ps
Cycle-to-cycle period jitter
Global
t
JIT(cc)
-150
150
-165
165
-165
165
ps
Duty cycle jitter
Global
t
JIT(duty)
-7575-90
90-9090
ps
Notes to Table 1–49:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL
output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
(3) The memory output clock jitter stated in Table 1–49 is applicable when an input jitter of 30 ps is applied.
(4) The clock jitter specification is characterized with 70% utilization, 266 MHz core clock frequency, and 12.5% design toggle rate. If your design
exceeds any of these conditions, the jitter specification of the design may not meet the above specification.
Table 1–50. OCT Calibration Block Specifications for Stratix IV Devices
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
20
MHz
TOCTCAL
Number of OCTUSRCLK clock cycles required for OCT RS/RT
calibration
—
1000
—
Cycles
TOCTSHIFT
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
—
28
—
Cycles
TRS_RT
Time required between the dyn_term_ctrl and oe signal
transitions in a bidirectional I/O buffer to dynamically switch
between OCT RS and RT
—2.5
—
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP4SGX530KH40C2ES 制造商:Altera Corporation 功能描述:FPGA Stratix
EP4SGX530KH40C2N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 21248 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX530KH40C2NES 制造商:Altera Corporation 功能描述:IC FPGA 744 I/O 1517HBGA 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 1517HBGA
EP4SGX530KH40C3 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 21248 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX530KH40C3ES 功能描述:IC STRATIX IV GX 530K 1517-HBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Stratix® IV GX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
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