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| 型號： | EPC4QC100N |
| 廠商： | Altera |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 4MBIT 100-PQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | EPC |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 4Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-1378 EPC4QC100N-ND |
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Page 16
Functional Description
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
Intel Flash-Based EPC Device Protection
In the absence of the lock bit protection feature in the EPC4, EPC8, and EPC16 devices
with Intel flash, Altera recommends four methods to protect the Intel Flash content in
EPC4, EPC8, and EPC16 devices. Any method alone is sufficient to protect the flash.
The methods are listed here in the order of descending protection level:
1. Using an RP# of less than 0.3 V on power-up and power-down for a minimum of
100 ns to a maximum 25 ms disables all control pins, making it impossible for a
write to occur.
2. Using VPP < VPPLK, where the maximum value of VPPLK is 1 V, disables writes.
VPP < VPPLK means programming or writes cannot occur. VPP is a programming
supply voltage input pin on the Intel flash. VPP is equivalent to the VCCW pin on
EPC devices.
3. Using a high CE# disables the chip. The requirement for a write is a low CE# and
low WE#. A high CE# by itself prevents writes from occurring.
4. Using a high WE# prevent writes because a write only occurs when the WE# is low.
Performing all four methods simultaneously is the safest protection for the flash
content.
The following lists the ideal power-up sequence:
1. Power up VCC.
2. Maintain VPP< VPPLK until VCC is fully powered up.
3. Power up VPP.
4. Drive RP# low during the entire power-up process. RP# must be released high
within 25 ms after VPP is powered up.
1 CE# and WE# must be high for the entire power-up sequence.
The following lists the ideal power-down sequence:
1. Drive RP# low for 100 ns before power-down.
2. Power down VPP < VPPLK.
3. Power down VCC.
4. Drive RP# low during the entire power-down process.
1 CE# and WE# must be high for the entire power-down sequence.
The RP# pin is not internally connected to the controller. Therefore, an external
loop-back connection between C-RP# and F-RP# must be made on the board even
when you are not using the external device to the RP# pin with the loop-back
connection. Always tri-state RP# when the flash is not in use.
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