參數(shù)資料
型號(hào)： EPC8QC100N
廠商： Altera
文件頁(yè)數(shù)： 16/36頁(yè)
文件大?。?/td> 0K
描述： IC CONFIG DEVICE 8MBIT 100-PQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 66
系列： EPC
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 8Mb
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 604 (CN2011-ZH PDF)
其它名稱： 544-1683
Pin Description
Page 23
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
Table 9. External Flash Interface Pins (Part 1 of 2)
Pin Name
Pin Type
Description
A[20..0]
Input
These pins are the address input to the flash memory for read and write
operations. The addresses are internally latched during a write cycle.
When the external flash interface is not used, leave these pins floating (with a few
exceptions (1)). These flash address, data, and control pins are internally
connected to the configuration controller.
In the 100-pin PQFP package, four address pins (A0, A1, A15, A16) are not
internally connected to the controller. These loop-back connections must be made
on the board between the C-A[] and F-A[] pins even when you are not using the
external flash interface. All other address pins are connected internal to the
package.
All address pins are connected internally in the 88-pin UFBGA package.
Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19,
and A18 in EPC4 devices are NC pins. These pins should be left floating on the
board.
DQ[15..0]
Bidirectional
This is the flash data bus interface between the flash memory and the controller.
The controller or an external source drives DQ[15..0] during the flash command
and the data write bus cycles. During the data read cycle, the flash memory drives
the DQ[15..0] to the controller or external device.
Leave these pins floating on the board when the external flash interface is not
used.
CE#
Input
Active low flash input pin that activates the flash memory when asserted. When it
is high, it deselects the device and reduces power consumption to standby levels.
This flash input pin is internally connected to the controller.
Leave this pin floating on the board when the external flash interface is not used.
RP# (1)
Input
Active low flash input pin that resets the flash when asserted. When high, it
enables normal operation. When low, it inhibits write operation to the flash
memory, which provides data protection during power transitions.
This flash input is not internally connected to the controller. Hence, an external
loop-back connection between C-RP# and F-RP# must be made on the board
even when you are not using the external flash interface.
When using the external flash interface, connect the external device to the RP# pin
with the loop back. Always tri-state RP# when the flash is not in use.
OE#
Input
Active-low flash-control input that is asserted by the controller or external device
during flash read cycles. When asserted, it enables the drivers of the flash output
pins.
Leave this pin floating on the board when the external flash interface is not used.
WE# (1)
Input
Active-low flash-write strobe asserted by the controller or external device during
flash write cycles. When asserted, it controls writes to the flash memory. In the
flash memory, addresses and data are latched on the rising edge of the WE# pulse.
This flash input is not internally connected to the controller. Hence, an external
loop-back connection between C-WE# and F-WE# must be made on the board
even when you are not using the external flash interface.
When using the external flash interface, connect the external device to the WE# pin
with the loop back.
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