參數(shù)資料
型號(hào)： EPC8QC100N
廠商： Altera
文件頁(yè)數(shù)： 34/36頁(yè)
文件大?。?/td> 0K
描述： IC CONFIG DEVICE 8MBIT 100-PQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 66
系列： EPC
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 8Mb
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 604 (CN2011-ZH PDF)
其它名稱： 544-1683
Functional Description
Page 7
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
Figure 1 shows a block diagram of the EPC device.
The EPC device features multiple configuration schemes. In addition to supporting
the traditional passive serial (PS) configuration scheme for a single device or a
serial-device chain, the EPC device features concurrent configuration and parallel
configuration. With the concurrent configuration scheme, up to eight PS device chains
can be configured simultaneously. In the FPP configuration scheme, 8-bits of data are
clocked into the FPGA during each cycle. These configuration schemes offer
significantly reduced configuration times over traditional schemes.
Furthermore, the EPC device features a dynamic configuration or page mode feature.
This feature allows you to dynamically reconfigure all the FPGAs in your system with
new images stored in the configuration memory. Up to eight different system
configurations or pages can be stored in the memory and selected using the
PGM[2..0]
pins. Your system can be dynamically reconfigured by selecting one of the
eight pages and initiating a reconfiguration cycle.
This page mode feature combined with the external flash interface allows remote and
local updates of system configuration data. The EPC devices are compatible with the
remote system configuration feature of the Stratix device.
f For more information, refer to the Remote System Configuration with Stratix &
Stratix GX Devices chapter in the Stratix Device Handbook.
Other user programmable features include:
■
Real-time decompression of configuration data
■
Programmable configuration clock (DCLK)
■
Flash ISP
■
Programmable POR delay (PORSEL)
Figure 1. EPC Device Block Diagram
Flash
FPGA
Controller
JTAG/ISP Interface
EPC Device
Shared Flash Interface
Shared Flash
Interface
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