- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19911 > EPCS16SI8N (Altera)IC CONFIG DEVICE 16MBIT 8-SOIC PDF資料下載
參數(shù)資料
| 型號(hào)： | EPCS16SI8N |
| 廠商： | Altera |
| 文件頁數(shù)： | 30/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 16MBIT 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | EPCS |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲(chǔ)容量： | 16Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-2567-5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Page 36
Pin Information
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Table 23 lists the pin description of the EPCS device.
Figure 23 shows the layout recommendation for vertical migration from the EPCS1
device to the EPCS128 device.
Table 23. EPCS Device Pin Description
Pin
Name
Pin Number
in 8-Pin
SOIC
Package
Pin Number
in 16-Pin
SOIC
Package
Pin Type
Description
DATA
2
8
Output
The DATA output signal transfers data serially out of the EPCS device
to the FPGA during the read operation or configuration. During the
read operation or configuration, the EPCS device is enabled by pulling
the nCS signal low. The DATA signal transitions on the falling edge of
the DCLK signal.
ASDI
5
15
Input
The ASDI signal is used to transfer data serially into the EPCS device.
This pin are also receiving data that are programmed into the EPCS
device. Data is latched on the rising edge of the DCLK signal.
nCS
1
7
Input
The nCS signal toggles at the beginning and the end of a valid
instruction. When this signal goes high, the device is deselected and
the DATA pin is tri-stated. When this signal goes low, the device is
enabled and in an active mode. After power up, the EPCS device
requires a falling edge on the nCS signal before the EPCS device
begins any operation.
DCLK
6
16
Input
The FPGA provides the DCLK signal. This signal provides the timing
for the serial interface. The data presented on the ASDI pin is latched
to the EPCS device on the rising edge of the DCLK signal. The data on
the DATA pin changes after the falling edge of the DCLK signal and is
latched into the FPGA on the next falling edge of the DCLK signal.
VCC
3, 7, 8
1, 2, 9
Power
Connect the power pins to a 3.3-V power supply.
GND
4
10
GND
Ground pin.
Figure 23. Layout Recommendation for Vertical Migration from the EPCS1 Device to the EPCS128
Device
Pi
n1
ID
Pin 1 ID
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACC26DRYN-S734 | CONN EDGECARD 52POS DIP .100 SLD |
| NCV59301DS33R4G | IC REG LDO 3.3V 3A D2PAK-5 |
| EBA10DTKT | CONN EDGECARD 20POS DIP .125 SLD |
| LT4250LCS8#PBF | IC CONTRLR HOTSWAP NEG 48V 8SOIC |
| ACC60DRTH-S13 | CONN EDGECARD 120PS .100 DIP SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPCS1N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述: |
| EPCS1SI8 | 功能描述:FPGA-配置存儲(chǔ)器 IC - Ser. Config Mem Flash 1Mb 40 MHz RoHS:否 制造商:Altera Corporation 存儲(chǔ)類型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| EPCS1SI8N | 功能描述:FPGA-配置存儲(chǔ)器 IC - Ser. Config Mem Flash 1Mb 40 MHz RoHS:否 制造商:Altera Corporation 存儲(chǔ)類型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| EPCS250 | 制造商:Electrolube 功能描述:COATING MASK PEELABLE 250 制造商:Electrolube 功能描述:COATING MASK, PEELABLE 250 |
| EPCS2PC1 | 制造商:Switchcraft 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。