參數(shù)資料
型號： EPCS1SI8N
廠商： Altera
文件頁數(shù)： 20/40頁
文件大小： 0K
描述： IC CONFIG DEVICE 1MBIT 8-SOIC
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 100
系列： EPCS
可編程類型： 系統(tǒng)內(nèi)可編程
存儲容量： 1Mb
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 管件
產(chǎn)品目錄頁面： 604 (CN2011-ZH PDF)
其它名稱： 544-1242-5
EPCS Device Memory Access
Page 27
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Figure 16 shows the instruction sequence of the erase bulk operation.
Erase Sector Operation
The erase sector operation code is b'1101 1000 and it lists the MSB first. This
operation allows you to erase a certain sector in the EPCS device by setting all the bits
inside the sector to 1 or 0xFF. This operation is useful if you want to access the unused
sectors as general purpose memory in your applications. You must execute the write
enable operation before the erase sector operation so that the write enable latch bit in
the status register is set to 1.
You can implement the erase sector operation by first driving the nCS signal low, then
you shift in the erase sector operation code, followed by the three address bytes of the
chosen sector on the ASDI pin. The three address bytes for the erase sector operation
can be any address inside the specified sector. For more information about the sector
address range, refer to Table 3 on page 7 through Table 7 on page 12. Drive the nCS
signal high after the eighth bit of the erase sector operation code has been latched in.
The device initiates the self-timed erase sector cycle immediately after the nCS signal is
driven high. For more information about the self-timed erase sector cycle time, refer to
the tES value in Table 16 on page 29.
You must account for this delay before accessing the memory contents. Alternatively,
you can check the write in progress bit in the status register by executing the read
status operation while the self-timed erase sector cycle is in progress. The write in
progress bit is set to 1 during the self-timed erase sector cycle and 0 when it is
complete. The write enable latch bit in the status register resets to 0 before the erase
cycle is complete.
Figure 17 shows the instruction sequence of the erase sector operation.
Figure 16. Erase Bulk Operation Timing Diagram
nCS
DCLK
ASDI
01234567
Operation Code
Figure 17. Erase Sector Operation Timing Diagram
Note to Figure 17:
(1) Address bit A[23] is a don't-care bit in the EPCS64 device. Address bits A[23..21] are don't-care bits in the EPCS16 device. Address bits
A[23..19]
are don't-care bits in the EPCS4 device. Address bits A[23..17] are don't-care bits in the EPCS1 device.
nCS
DCLK
ASDI
01234567
89
28
29
30
31
Operation Code
24-Bit Address (1)
23
22
3
2
1
0
MSB
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EPCS4SI8 功能描述:FPGA-配置存儲器 IC - Ser. Config Mem Flash 4Mb 40 MHz RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20
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