Figure 7 shows how an n-bit full adder can be implemente" />
參數(shù)資料
型號: EPF10K100ARI240-3
廠商: Altera
文件頁數(shù): 37/128頁
文件大?。?/td> 0K
描述: IC FLEX 10KA FPGA 100K 240-RQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告: Package Change 30/Jun/2010
標(biāo)準(zhǔn)包裝: 24
系列: FLEX-10K®
LAB/CLB數(shù): 624
邏輯元件/單元數(shù): 4992
RAM 位總計(jì): 24576
輸入/輸出數(shù): 189
門數(shù): 158000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 240-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 240-RQFP(32x32)
其它名稱: 544-1251
16
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 7 shows how an n-bit full adder can be implemented in n +1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can either be bypassed for simple adders or
be used for an accumulator function. The carry chain logic generates the
carry-out signal, which is routed directly to the carry-in signal of the next-
higher-order bit. The final carry-out signal is routed to an LE, where it can
be used as a general-purpose signal.
Figure 7. Carry Chain Operation (n-bit Full Adder)
LUT
a1
b1
Carry Chain
s1
LE1
Register
a2
b2
Carry Chain
s2
LE2
Register
Carry Chain
sn
LEn
Register
an
bn
Carry Chain
Carry-Out
LEn + 1
Register
Carry-In
LUT
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