參數(shù)資料
型號: EPF10K100ARI240-3
廠商: Altera
文件頁數(shù): 83/128頁
文件大?。?/td> 0K
描述: IC FLEX 10KA FPGA 100K 240-RQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告: Package Change 30/Jun/2010
標(biāo)準(zhǔn)包裝: 24
系列: FLEX-10K®
LAB/CLB數(shù): 624
邏輯元件/單元數(shù): 4992
RAM 位總計: 24576
輸入/輸出數(shù): 189
門數(shù): 158000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 240-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 240-RQFP(32x32)
其它名稱: 544-1251
58
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 26. FLEX 10K Device IOE Timing Model
Figure 27. FLEX 10K Device EAB Timing Model
Figures 28 shows the timing model for bidirectional I/O pin timing.
Data-In
I/O Register
Delays
tIOCO
tIOCOMB
tIOSU
tIOH
tIOCLR
Output Data
Delay
tIOD
I/O Element
Control Delay
tIOC
Input Register Delay
tINREG
Output
Delays
tOD1
tOD2
tOD3
tXZ
tZX1
tZX2
tZX3
I/O Register
Feedback Delay
tIOFD
Input Delay
tINCOMB
Clock Enable
Clear
Data Feedback
into FastTrack
Interconnect
Clock
Output Enable
EAB Data Input
Delays
tEABDATA1
tEABDATA2
Data-In
Write Enable
Input Delays
tEABWE1
tEABWE2
EAB Clock
Delay
tEABCLK
Input Register
Delays
tEABCO
tEABBYPASS
tEABSU
tEABH
tEABCH
tEABCL
RAM/ROM
Block Delays
tAA
tDD
tWP
tWDSU
tWDH
tWASU
tWAH
tWO
Output Register
Delays
tEABCO
tEABBYPASS
tEABSU
tEABH
tEABCH
tEABCL
tEABOUT
Address
WE
Input Register
Clock
Output Register
Clock
Data-Out
EAB Output
Delay
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