參數(shù)資料
型號: EPF10K30AFC484-1
廠商: Altera
文件頁數(shù): 31/128頁
文件大?。?/td> 0K
描述: IC FLEX 10KA FPGA 30K 484-FBGA
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 60
系列: FLEX-10K®
LAB/CLB數(shù): 216
邏輯元件/單元數(shù): 1728
RAM 位總計: 12288
輸入/輸出數(shù): 246
門數(shù): 69000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 484-BGA
供應商設備封裝: 484-FBGA(23x23)
126
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Multiple FLEX 10K devices can be configured in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device.
Device Pin-
Outs
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
Revision
History
The information contained in the FLEX 10K Embedded Programmable Logic
Device Family Data Sheet version 4.2 supersedes information published in
previous versions.
Version 4.2 Changes
The following change was made to version 4.2 of the FLEX 10K Embedded
Programmable Logic Device Family Data Sheet: updated Figure 13.
Version 4.1 Changes
The following changes were made to version 4.1 of the FLEX 10K
Embedded Programmable Logic Device Family Data Sheet.
Updated General Description section
Updated I/O Element section
Updated SameFrame Pin-Outs section
Updated Figure 16
Updated Tables 13 and 116
Added Note 9 to Table 19
Added Note 10 to Table 24
Added Note 10 to Table 28
Table 116. Data Sources for Configuration
Configuration Scheme
Data Source
Configuration device
EPC1, EPC2, EPC16, or EPC1441 configuration device
Passive serial (PS)
BitBlaster, MasterBlaster, or ByteBlasterMV download cable, or
serial data source
Passive parallel asynchronous (PPA)
Parallel data source
Passive parallel synchronous (PPS)
Parallel data source
JTAG
BitBlaster, MasterBlaster, or ByteBlasterMV download cable, or
microprocessor with Jam STAPL file or Jam Byte-Code file
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