參數(shù)資料
型號： EPF10K50EQC240-1N
廠商： Altera
文件頁數(shù)： 10/100頁
文件大?。?/td> 0K
描述： IC FLEX 10KE FPGA 50K 240-PQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 24
系列： FLEX-10KE®
LAB/CLB數(shù)： 360
邏輯元件/單元數(shù)： 2880
RAM 位總計： 40960
輸入/輸出數(shù)： 189
門數(shù)： 199000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 240-BFQFP
供應(yīng)商設(shè)備封裝： 240-PQFP（32x32）
Altera Corporation
17
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks,
the other two can be used for clear/preset control. The LAB clocks can be
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typically used for global clock, clear, or preset signals because they
provide asynchronous control with very low skew across the device. If
logic is required on a control signal, it can be generated in one or more LE
in any LAB and driven into the local interconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the FLEX 10KE architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
four-input LUT, which is a function generator that can quickly compute
any function of four variables. In addition, each LE contains a
programmable flipflop with a synchronous clock enable, a carry chain,
and a cascade chain. Each LE drives both the local and the FastTrack
Interconnect routing structure (see Figure 8).
Figure 8. FLEX 10KE Logic Element
LAB Local
Interconnect
Carry-In
Clock
Select
Carry-Out
Look-Up
Table
(LUT)
Clear/
Preset
Logic
Carry
Chain
Cascade
Chain
Cascade-In
Cascade-Out
FastTrack
Interconnect
Programmable
Register
PRN
CLRN
DQ
ENA
Register Bypass
data1
data2
data3
data4
labctrl1
labctrl2
labctrl4
labctrl3
Chip-Wide
Reset
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K50EQC240-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50EQC240-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50EQC2403 制造商:n/a 功能描述:_
EPF10K50EQC240-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50EQC240-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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