Notes to tables: (1) Internal timing parameters cannot be measured " />
參數(shù)資料
型號(hào)： EPF8820AQC208-4
廠商： Altera
文件頁(yè)數(shù)： 28/62頁(yè)
文件大?。?/td> 0K
描述： IC FLEX 8000A FPGA 8K 208-PQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 72
系列： FLEX 8000
LAB/CLB數(shù)： 84
邏輯元件/單元數(shù)： 672
輸入/輸出數(shù)： 152
門數(shù)： 8000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
產(chǎn)品目錄頁(yè)面： 602 (CN2011-ZH PDF)
其它名稱： 544-2264
34
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
Internal timing parameters cannot be measured explicitly. They are worst-case delays based on testable and
external parameters specified by Altera. Internal timing parameters should be used for estimating device
performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case
performance.
(2)
These values are specified in Table 10 on page 28 or Table 14 on page 29.
(3)
For the tOD3 and tZX3 parameters, VCCIO = 3.3 V or 5.0 V.
(4)
The tROW and tDIN_D delays are worst-case values for typical applications. Post-compilation timing simulation or
timing analysis is required to determine actual worst-case performance.
(5)
External reference timing characteristics are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
(6)
For more information on test conditions, see Application Note 76 (Understanding FLEX 8000 Timing).
(7)
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies to global and non-global clocking, and for LE and I/O element registers.
The FLEX 8000 timing model shows the delays for various paths and
functions in the circuit. See Figure 19. This model contains three distinct
parts: the LE; the IOE; and the interconnect, including the row and column
FastTrack Interconnect, LAB local interconnect, and carry and cascade
interconnect paths. Each parameter shown in Figure 19 is expressed as a
worst-case value in Tables 22 through 49. Hand-calculations that use the
FLEX 8000 timing model and these timing parameters can be used to
estimate FLEX 8000 device performance. Timing simulation or timing
analysis after compilation is required to determine the final worst-case
performance. Table 21 summarizes the interconnect paths shown in
f For more information on timing parameters, go to Application Note 76
Table 19. FLEX 8000 Interconnect Timing Parameters
Symbol
Parameter
tLABCASC
Cascade delay between LEs in different LABs
tLABCARRY
Carry delay between LEs in different LABs
tLOCAL
LAB local interconnect delay
tROW
Row interconnect routing delay (4)
tCOL
Column interconnect routing delay
tDIN_C
Dedicated input to LE control delay
tDIN_D
Dedicated input to LE data delay (4)
tDIN_IO
Dedicated input to IOE control delay
Table 20. FLEX 8000 External Reference Timing Characteristics
Symbol
Parameter
tDRR
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local interconnects (6)
tODH
Output data hold time after clock (7)
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