參數(shù)資料
型號： EPM3512AFI256-10N
廠商： Altera
文件頁數(shù)： 9/46頁
文件大小： 0K
描述： IC MAX 3000A CPLD 512 256-FBGA
標(biāo)準(zhǔn)包裝： 90
系列： MAX® 3000A
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目： 32
宏單元數(shù)： 512
門數(shù)： 10000
輸入/輸出數(shù)： 208
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
包裝： 托盤
Altera Corporation
17
MAX 3000A Programmable Logic Device Family Data Sheet
Programming
with External
Hardware
MAX 3000A devices can be programmed on Windows–based PCs with an
Altera Logic Programmer card, MPU, and the appropriate device adapter.
The MPU performs continuity checking to ensure adequate electrical
contact between the adapter and the device.
f For more information, see the Altera Programming Hardware Data Sheet.
The Altera software can use text– or waveform–format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also provide programming support for Altera devices.
f For more information, see Programming Hardware Manufacturers.
IEEE Std.
1149.1 (JTAG)
Boundary–Scan
Support
MAX 3000A devices include the JTAG BST circuitry defined by IEEE
Std. 1149.1–1990. Table 7 describes the JTAG instructions supported by
MAX 3000A devices. The pin-out tables found on the Altera web site
(http://www.altera.com) or the Altera Digital Library show the location of
the JTAG control pins for each device. If the JTAG interface is not
required, the JTAG pins are available as user I/O pins.
Table 7. MAX 3000A JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins
EXTEST
Allows the external circuitry and board–level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins
BYPASS
Places the 1–bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation
IDCODE
Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO
USERCODE
Selects the 32–bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO
ISP Instructions
These instructions are used when programming MAX 3000A devices via the JTAG ports
with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL
file, JBC file, or SVF file via an embedded processor or test equipment
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參數(shù)描述
EPM3512AQC208-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 3000A 512 Macro 172 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM3512AQC208-10N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 3000A 512 Macro 172 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM3512AQC208-7 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 3000A 512 Macro 172 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM3512AQC208-7N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 3000A 512 Macro 172 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM3512AQI208-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 3000A 512 Macro 172 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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