參數(shù)資料
型號: EPM7064LC44-7
廠商: Altera
文件頁數(shù): 45/66頁
文件大?。?/td> 0K
描述: IC MAX 7000 CPLD 64 44-PLCC
標準包裝: 390
系列: MAX® 7000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 4
宏單元數(shù): 64
門數(shù): 1250
輸入/輸出數(shù): 36
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.58x16.58)
包裝: 管件
其它名稱: 544-2299-5
Altera Corporation
5
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture supports 100% TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from
PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices
are available in a wide range of packages, including PLCC, PGA, PQFP,
RQFP, and TQFP packages. See Table 5.
Notes:
(1)
When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins
become JTAG pins.
(2)
Perform a complete thermal analysis before committing a design to this device package. For more information, see
MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a
variety of independent combinatorial and sequential logic functions. The
devices can be reprogrammed for quick and efficient iterations during
design development and debug cycles, and can be programmed and
erased up to 100 times.
Table 5. MAX 7000 Maximum User I/O Pins
Device
44-
Pin
PLCC
44-
Pin
PQFP
44-
Pin
TQFP
68-
Pin
PLCC
84-
Pin
PLCC
100-
Pin
PQFP
100-
Pin
TQFP
160-
Pin
PQFP
160-
Pin
PGA
192-
Pin
PGA
208-
Pin
PQFP
208-
Pin
RQFP
EPM7032
36
EPM7032S
36
EPM7064
36
52
68
EPM7064S
36
68
EPM7096
52
64
76
EPM7128E
68
84
100
EPM7128S
68
84
84 (2)
100
EPM7160E
64
84
104
EPM7160S
64
84 (2)
104
EPM7192E
124
EPM7192S
124
EPM7256E
132 (2)
164
EPM7256S
164 (2)
164
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