Notes: (1) Only available in MAX 70" />
參數(shù)資料
型號: EPM7256SRI208-10N
廠商: Altera
文件頁數(shù): 22/66頁
文件大?。?/td> 0K
描述: IC MAX 7000 CPLD 256 208-RQFP
產(chǎn)品變化通告: Package Change 30/Jun/2010
標準包裝: 24
系列: MAX® 7000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 10.0ns
電壓電源 - 內(nèi)部: 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數(shù)目: 16
宏單元數(shù): 256
門數(shù): 5000
輸入/輸出數(shù): 164
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 208-RQFP(28x28)
包裝: 托盤
Altera Corporation
29
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 12. MAX 7000 Timing Model
Notes:
(1)
Only available in MAX 7000E and MAX 7000S devices.
(2)
Not available in 44-pin devices.
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Figure 13 shows the internal timing
relationship of internal and external delay parameters.
Logic Array
Delay
t LAD
Output
Delay
t OD3
t OD2
t OD1
t XZ
Z
t X1
t ZX2
t ZX3
Input
Delay
t IN
Register
Delay
t SU
t H
t PRE
t CLR
t RD
t COMB
t FSU
t FH
PIA
Delay
t PIA
Shared
Expander Delay
t SEXP
Register
Control Delay
t LAC
t IC
t EN
I/O
Delay
t IO
Global Control
Delay
t GLOB
Internal Output
Enable Delay
t IOE
Parallel
Expander Delay
t PEXP
Fast
Input Delay
t FIN
(1)
(2)
(1)
(2)
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