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參數(shù)資料
| 型號： | EV-ADF4156SD1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADF4156 |
| 標準包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4156 |
| 主要屬性： | 單路分數(shù)-N PLL |
| 次要屬性： | 6.2GHz |
| 已供物品： | 板，CD |
Data Sheet
ADF4156
Rev. E | Page 19 of 24
ADF4156
CP
MUXOUT
C1
C2
R2
R1
R1A
C3
VCO
058
63-
0
23
Figure 22. Topology 1—Fast-Lock Loop Filter Topology
ADF4156
CP
MUXOUT
C1
C2
R2
R1
R1A
C3
VCO
058
63-
0
24
Figure 23. Topology 2—Fast-Lock Loop Filter Topology
SPUR MECHANISMS
This section describes the three spur mechanisms that arise
with a fractional-N synthesizer and how to minimize these
spurs in the ADF4156.
Fractional Spurs
The fractional interpolator in the ADF4156 is a third-order Σ-Δ
modulator with a modulus (MOD) that is programmable to any
integer value from 2 to 4095. In low spur mode (dither enabled),
the minimum allowable value of MOD is 50. The Σ-Δ modulator
is clocked at the PFD reference rate (fPFD) that allows PLL output
frequencies to be synthesized at a channel step resolution of
fPFD/MOD.
In low noise mode (dither off), the quantization noise from the
Σ-Δ modulator appears as fractional spurs. The interval between
spurs is fPFD/L, where L is the repeat length of the code sequence
in the digital Σ-Δ modulator. For the third-order modulator used
in the ADF4156, the repeat length depends on the value of MOD,
as listed in Table 7.
Table 7. Fractional Spurs with Dither Off
Condition
Repeat
Length
Spur Interval
If MOD is divisible by 2, but not 3
2 × MOD
Channel step/2
If MOD is divisible by 3, but not 2
3 × MOD
Channel step/3
If MOD is divisible by 6
6 × MOD
Channel step/6
Otherwise
MOD
Channel step
In low spur mode (dither enabled), the repeat length is extended
to 221 cycles, regardless of the value of MOD, which makes the
quantization error spectrum look like broadband noise. As a
result, the in-band phase noise at the PLL output can be degraded
by as much as 10 dB. Therefore, for lowest noise, keeping dither
off is a better choice, particularly when the final loop bandwidth is
low enough to attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation is interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (as is the case
with fractional-N synthesizers), spur sidebands appear on the
VCO output spectrum at an offset frequency that corresponds
to the beat note or the difference in frequency between an
integer multiple of the reference and the VCO frequency.
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the
reference, where the difference frequency can be inside the loop
bandwidth, hence the name integer boundary spurs.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism that
bypasses the loop can cause a problem. One such mechanism is
feedthrough of low levels of switching noise from the on-chip
reference through the RFIN pin and back to the VCO, resulting
in reference spur levels as high as 90 dBc. Care should be taken in
the PCB layout to ensure that the VCO is well separated from the
input reference to avoid a possible feedthrough path on the board.
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
With dither off, the fractional spur pattern due to the quantization
noise of the Σ-Δ modulator also depends on the phase word set
as the starting point of the modulator. Setting the Σ-Δ reset bit
(DB14 in Register R3) to 0 ensures that this starting point is used
for the Σ-Δ modulator on every write to Register R0.
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Therefore,
a look-up table of phase values corresponding to each frequency
can be constructed for use when programming the ADF4156.
The evaluation software has a sweep function to sweep the
phase word so that the user can observe the spur levels on a
spectrum analyzer.
If a look-up table is not used, keep the phase word at a constant
value to ensure consistent spur levels on a particular frequency.
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參數(shù)描述 |
|---|---|
| EV-ADF4157SD1Z | 功能描述:BOARD EVAL FOR ADF4157 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EV-ADF4159EB1Z | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADF4159 |
| EV-ADF4159EB2Z | 制造商:Analog Devices 功能描述:13GHZFRAC-NPLL+ADF55XXVCO+3VADM - Boxed Product (Development Kits) |
| EV-ADF4159EB3Z | 制造商:Analog Devices 功能描述:EVALUATIONBOARD - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADF4159 制造商:Analog Devices 功能描述:Clock & Timer Development Tools ADF4159 EVAL BRD |
| EV-ADF4360-0EB1Z | 功能描述:BOARD EVAL FOR ADF4360-0 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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