參數(shù)資料
型號(hào)： EV-ADF4156SD1Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/24頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADF4156
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4156
主要屬性： 單路分?jǐn)?shù)-N PLL
次要屬性： 6.2GHz
已供物品： 板，CD
ADF4156
Data Sheet
Rev. E | Page 8 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. While the
device is operating, SW1 and SW2 are usually closed switches
and SW3 is open. When a power-down is initiated, SW3 is
closed and SW1 and SW2 are opened. This ensures that the
REFIN pin is not loaded while the device is powered down.
BUFFER
TO R-COUNTER
REFIN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
05863-
005
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
two-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
AGND
AVDD
RFINB
RFINA
2k
2k
05863-
006
Figure 12. RF Input Stage
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R-counter, enable generating output frequencies that are spaced
by fractions of the phase frequency detector (PFD). See the RF
Synthesizer: A Worked Example section for more information.
The RF VCO frequency (RFOUT) equation is
RFOUT = FPFD × (INT + (FRAC/MOD))
(1)
where RFOUT is the output frequency of an external voltage-
controlled oscillator (VCO).
FPFD = REFIN × [(1 + D)/(R × (1 + T))]
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
T is the REFIN divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
INT is the preset divide ratio of the binary 12-bit counter
(23 to 4095).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD 1).
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N-DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N-COUNTER
05863-
007
Figure 13. RF INT Divider
RF R-COUNTER
The 5-bit RF R-counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 32 are allowed.
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