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參數(shù)資料
| 型號： | EV-ADF4360-7EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADF4360-7 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-7 |
| 主要屬性： | 帶 VCO 的單路整數(shù)-N PLL |
| 次要屬性： | 900MHz，200kHz PFD |
| 已供物品： | 板，纜線，CD |
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Data Sheet
ADF4360-7
Rev. D | Page 21 of 28
APPLICATIONS
FREQUENCY GENERATOR
The wide frequency range of the AD4360-7, plus the on-chip
divider, make it an ideal choice for implementing any general
purpose clock generator or LO.
To implement a clock generator in the FM band, it is necessary
to use an external divider. The ADF4007 contains a hardware-
programmable N divider, allowing division ratios of 8, 16, 32,
and 64. This divided-down signal is accessed from the MUX-
OUT pin of the ADF4007.
The minimum frequency that can be fed to the ADF4007 is
500 MHz. Therefore, 2.2 nH inductors were used to set the
fundamental frequency of oscillation at 1 GHz, with a range
from 950 MHz to 1100 MHz.
This allows frequencies as low as 8 MHz and as high as
137 MHz to be generated using a single system. In the circuit
drawn in Figure 23, the ADF4360-7 is being used to generate
1024 MHz, and the ADF4007 is being used to divide by 8. To
provide a channel spacing of 100 kHz, a PFD frequency of
800 kHz is used for the ADF4360-7 PLL. The loop bandwidth
is chosen to be 20 kHz.
The output range of the system in Figure 23 is approximately
120 MHz to 135 MHz. The output phase noise is 104 dBc/Hz
at 1 kHz offset. Using different inductor values allows the
ADF4360-7 to be used to synthesize any different range of
frequencies over the operation of the part (235 MHz to
1800 MHz).
ADF4007
TO LO
PORT
VP
REFIN
RFINA
M2
M1
CP
RSET
MUXOUT
PHASE
FREQUENCY
DETECTOR
R COUNTER
÷2
VDD
RFINB
N2
N1
04441-027
SPI
COMPATIBLE
SERIAL
BUS
ADF4360-7
VVCO
CPGND
AGND DGND
GND
CPGND
L1 L2 RF
OUTB
RFOUTA
FREFIN
CP
1nF
470pF
2.2nH
220pF
6.8nF
51
51
51
4.7k
100pF
1nF
10
F
4.7k
6.2k
13k
RSET
CC
LE
DATA
CLK
REFIN
CN
VTUNE
DVDD AVDD CE MUXOUT
5
4
24
7
20
23
2
21
6
14
16
17
18
19
13
1
3
8
9
10
11 22
15
12
VDD
LOCK
DETECT
CHARGE
PUMP
MUX
N COUNTER
÷8, ÷16,
÷32, ÷64
Figure 23. Frequency Generator
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