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參數(shù)資料
型號(hào)： EV-ADF4360-7EB1Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/28頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR ADF4360-7
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4360-7
主要屬性： 帶 VCO 的單路整數(shù)-N PLL
次要屬性： 900MHz，200kHz PFD
已供物品： 板，纜線(xiàn)，CD
ADF4360-7
Data Sheet
Rev. D | Page 12 of 28
After band selection, normal PLL action resumes. The
value of KV is determined by the value of inductors used
(see the Choosing the Correct Inductance section). If divide-by-
2 operation has been selected (by programming DIV2 [DB22]
high in the N counter latch), the value is halved. The ADF4360
family contains linearization circuitry to minimize any variation
of the product of ICP and KV.
The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360 family are con-
nected to the collectors of an NPN differential pair driven by
buffered outputs of the VCO, as shown in Figure 21. To allow
the user to optimize the power dissipation vs. the output power
requirements, the tail current of the differential pair is pro-
grammable via Bits PL1 and PL2 in the control latch. Four cur-
rent levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. The-
se levels give output power levels of 14 dBm, 11 dBm,
8 dBm, and 5 dBm, respectively, using a 50 Ω resistor to VDD
and ac coupling into a 50 Ω load. Alternatively, both outputs
can be combined in a 1 + 1:1 transformer or a 180° microstrip
coupler (see the Output Matching section).
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD.
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
mute-till-lock detect (MTLD) bit in the control latch.
VCO
RFOUTARFOUTB
BUFFER/
DIVIDE BY 2
04441-021
Figure 21. Output Stage ADF4360-7
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