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參數(shù)資料
| 型號： | EVAL-AD1955EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD1955 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD1955 |
| 相關(guān)產(chǎn)品： | AD1955ARSZRL-ND - IC DAC AUDIO 16-24BIT 28SSOP AD1955ARSZ-ND - IC DAC AUDIO MULTIBIT 28-SSOP |
REV. 0
–14–
AD1955
For example, with the stereo circuits given in Figures 7 through
10, this gives:
12 0
2 80
3 24
2 80
2 00
1 98
.
– ..
.
VV
mA
VK
k
[]
+
()
[] =
A 2.00 k
resistor is used.
The supply used should be as quiet as possible.
Serial Control Port
The AD1955 has an SPI compatible control port to permit pro-
gramming the internal control registers. The SPI control port is
a 3-wire serial port. Its format is similar to the Motorola SPI
format except that the input data-word is 16 bits wide. The serial
bit clock may be completely asynchronous to the sample rate of the
DAC. The following figure shows the format of the SPI signal
Note that the CCLK may be continuous or a 16-clock burst.
SPI REGISTER DEFINITIONS
Table I. DAC Control Register 0
Bit
Description
Value
Definition
15
Power-Down
0
Operation
1Powered Down
14
Mute
0
Not Muted
1
Muted
13:12
Data Format
00
PCM
01
External DF
10
SACD Slave
11
SACD Master
11:10
Output Format
00
Stereo
01
Not Allowed
10
Mono Left
11
Mono Right
9:8
PCM Sample Rate
00
48 kHz
01
96 kHz
10
192 kHz
11
Reserved
7:6
De-Emphasis Curve
00
None
Select
01
44.1 kHz
10
32 kHz
11
48 kHz
5:4
PCM/EF Serial Data
00
I
2S
Format
01
Right-Justified
10
DSP
11
Left-Justified
3:2
PCM/EF Serial Data
00
24 bits
Width
01
20 bits
10
18 bits
11
16 bits
1:0
SPI Register Address
00
Default = 0
Table II. DAC Control Register 1
Bit
Description
Value
Definition
10:9
MCLK Mode
00
256
fS
01
512
fS
10
768
fS
11
Reserved
8Zero Flag Polarity
0
Active High
1Active Low
7SACD Bit Rate
0
64
fS
1
128
fS
6SACD Mode
0
Normal
1
Phase Mode
5:4
SACD Phase Select
00
Phase 0
01
Phase 1
10
Phase 2
11
Phase 3
3SACD Bit Inversion
0
Normal
1
Inverted
2SACD MCLK to
0
Rising Edge
BCLK Phase
1
Falling Edge
1:0
SPI Register Address
01
Default = 0
Table III. DAC Volume Registers
Bit
Description
Value
Definition
14-Bit
15:2
Volume
Unsigned
1:0
SPI Register Address
10
Left Volume
11
Right Volume
Default = Full Volume
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1955EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD1955 STEREO DIGITAL AUDIO |
| EVAL-AD1958EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:PLL/Multibit DAC |
| EVAL-AD1959EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:PLL/Multibit DAC |
| EVAL-AD1970EB | 制造商:Analog Devices 功能描述:EVAL BD BTSC ENCODER W INTEGRATED CODEC - Bulk |
| EVAL-AD1974AZ | 功能描述:BOARD EVAL FOR AD1974 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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