fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT
參數(shù)資料
型號: EVAL-AD1955EBZ
廠商: Analog Devices Inc
文件頁數(shù): 7/24頁
文件大小: 0K
描述: BOARD EVAL FOR AD1955
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 2
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: 串行
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: AD1955
相關(guān)產(chǎn)品: AD1955ARSZRL-ND - IC DAC AUDIO 16-24BIT 28SSOP
AD1955ARSZ-ND - IC DAC AUDIO MULTIBIT 28-SSOP
REV. 0
AD1955
–15–
1/
fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
fS EXCEPT FOR DSP MODE, WHICH IS 2
fS.
3. BCLK FREQUENCY IS NORMALLY 64
LRCLK BUT MAY BE OPERATED IN BURST MODE.
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
I2S MODE –16 TO 24 BITS PER CHANNEL
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LEFT-JUSTIFIED MODE – 16 TO 24 BITS PER CHANNEL
DSP MODE – 16 TO 24 BITS PER CHANNEL
MSB
LSB
Figure 1. Supported Serial Data Formats
tDLS
BCLK
L/
RCLK
SDATA
LEFT-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
LSB
SDATA
I2S-JUSTIFIED
MODE
tDBH
tDBP
tDBL
tDDS
MSB
MSB-1
tDDH
tDDS
MSB
tDDH
tDDS
tDDH
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Data Port Timing
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