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參數(shù)資料
| 型號： | EVAL-AD2S1205SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD2S1205 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，旋轉(zhuǎn)變壓至數(shù)字 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD2S1205 |
| 主要屬性： | 12 位分辨率，最大 1250 rps 或 1024 脈沖/反向 |
| 已供物品： | 板 |
AD2S1205
Rev. A | Page 6 of 20
06
33
9-
0
02
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RE
F
O
UT
44
RE
F
BY
P
43
Co
sL
O
40
Si
n
L
O
38
AG
ND
42
AG
ND
36
AV
DD
39
EX
C
35
EX
C
34
Co
s
41
Si
n
37
DVDD 1
RD
2
CS
3
SAMPLE
4
RDVEL
5
SOE
6
DB11/SO
7
DB10/SCLK
8
DB9
9
DB8 10
DB7 11
RESET
33
FS2
32
FS1
31
LOT
30
DOS
29
AD2S1205
TOP VIEW
(Not to Scale)
DIR
28
NM
27
B
26
A
25
CPO
24
DGND
23
DB6
12
DB5
13
DB4
14
DB3
15
DG
ND
16
DV
DD
17
DB2
18
DB1
19
DB0
20
X
TA
L
O
U
T
21
CL
KI
N
22
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 17
DVDD
Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD2S1205. The
AVDD and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even
on a transient basis.
2
RD
Edge-Triggered Logic Input. This pin acts as a frame synchronization signal and output enable. The output buffer is
enabled when CS and RD are held low.
3
CS
Chip Select. Active low logic input. The device is enabled when CS is held low.
4
SAMPLE
Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and
velocity registers, respectively, after a high-to-low transition on the SAMPLE signal.
5
RDVEL
Read Velocity. Logic input. RDVEL input is used to select between the angular position register and the angular
velocity register. RDVEL is held high to select the angular position register and low to select the angular
velocity register.
6
SOE
Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is
selected by holding the SOE pin low, and the parallel interface is selected by holding the SOE pin high.
7
DB11/SO
Data Bit 11/Serial Data Output Bus. When the SOE pin is high, this pin acts as DB11, a three-state data output pin
controlled by CS and RD. When the SOE pin is low, this pin acts as SO, the serial data output bus controlled by CS
and RD. The bits are clocked out on the rising edge of SCLK.
8
DB10/SCLK
Data Bit 10/Serial Clock. In parallel mode this pin acts as DB10, a three-state data output pin controlled by CS and RD.
In serial mode this pin acts as the serial clock input.
9 to 15
DB9 to DB3
Data Bit 9 to Data Bit 3. Three-state data output pins controlled by CS and RD.
16, 23
DGND
Digital Ground. These pins are ground reference points for digital circuitry on the AD2S1205. All digital input
signals should be referred to this DGND voltage. Both of these pins can be connected to the AGND plane of a
system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V
apart, even on a transient basis.
18 to 20
DB2 to DB0
Data Bit 2 to Data Bit 0. Three-state data output pins controlled by CS and RD.
21
XTALOUT
Crystal Output. To achieve the specified dynamic performance, an external crystal is recommended at the CLKIN and
XTALOUT pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%.
22
CLKIN
Clock Input. To achieve the specified dynamic performance, an external crystal is recommended at the CLKIN and
XTALOUT pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%.
24
CPO
Charge-Pump Output. Analog output. A 204.8 kHz square wave output with a 50% duty cycle is available at the
CPO output pin. This square wave output can be used for negative rail voltage generation or to create a VCC rail.
25
A
Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
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