參數(shù)資料
型號: EVAL-AD5110SDZ
廠商: Analog Devices Inc
文件頁數(shù): 4/28頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD5110
標準包裝: 1
主要目的: 數(shù)字電位器
嵌入式:
已用 IC / 零件: AD5110
主要屬性: 1 通道,128 位置
次要屬性: I²C 接口
已供物品: 板,CD
AD5110/AD5112/AD5114
Data Sheet
Rev. B | Page 12 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
AD5110/
AD5112/
AD5114
3
W
4
B
1
VDD
2
A
6 SCL
5 GND
8 VLOGIC
7 SDA
09582-
004
NOTES
1. THE EXPOSED PAD IS INTERNALLY FLOATING.
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
V
DD
Positive Power Supply; 2.3 V to 5.5 V. This pin should be decoupled with 0.1 F ceramic capacitors and 10 F
capacitors.
2
A
Terminal A of RDAC. GND ≤ V
A ≤ VDD.
3
W
Wiper Terminal of RDAC. GND ≤ V
W ≤ VDD.
4
B
Terminal B of RDAC. GND ≤ V
B ≤ VDD.
5
GND
Ground Pin, Logic Ground Reference.
6
SCL
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit input
registers.
7
SDA
Serial Data Line. This pin is used in conjunction with the SCL line to clock data into or out of the 16-bit input
registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up
resistor.
8
V
LOGIC
Logic Power Supply; 1.8 V to V
DD. This pin should be decoupled with 0.1 F ceramic capacitors and 10 F
capacitors.
EPAD
Exposed Pad. The exposed pad is internally floating.
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