VDD
參數(shù)資料
型號(hào)： EVAL-AD5161EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5161
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD5161
Rev. B | Page 5 of 20
TIMING CHARACTERISTICS—5 k, 10 k, 50 k, 100 k VERSIONS
VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
SPI INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts)
Clock Frequency
f
CLK
25
MHz
Input Clock Pulsewidth
t
CH, tCL
Clock level high or low
20
ns
Data Setup Time
t
DS
5
ns
Data Hold Time
t
DH
5
ns
CS Setup Time
t
CSS
15
ns
CS High Pulsewidth
t
CSW
40
ns
CLK Fall to CS Fall Hold Time
t
CSH0
0
ns
CLK Fall to CS Rise Hold Time
t
CSH1
0
ns
CS Rise to Clock Rise Setup
t
CS1
10
ns
I2C INTERFACE TIMING CHARACTERISTICS6, 11 (Specifications Apply to All Parts)
SCL Clock Frequency
f
SCL
400
kHz
t
BUF Bus Free Time between STOP and START
t
1
1.3
s
t
HD;STA Hold Time (Repeated START)
t
2
After this period, the first clock pulse is
generated.
0.6
s
t
LOW Low Period of SCL Clock
t
3
1.3
s
t
HIGH High Period of SCL Clock
t
4
0.6
50
s
t
SU;STA Setup Time for Repeated START Condition
t
5
0.6
s
t
HD;DAT Data Hold Time
t
6
0.9
s
t
SU;DAT Data Setup Time
t
7
100
ns
t
F Fall Time of Both SDA and SCL Signals
t
8
300
ns
t
R Rise Time of Both SDA and SCL Signals
t
9
300
ns
t
SU;STO Setup Time for STOP Condition
t
10
0.6
s
NOTES
1 Typical specifications represent average readings at +25°C and V
DD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 V
AB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at V
W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 P
DISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use V
DD = 5 V.
10 See timing diagram for location of measured values. All input control voltages are specified with t
R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
11 See timing diagrams for locations of measured values.
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