參數(shù)資料
型號(hào)： EVAL-AD5161EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5161
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD5161
Rev. B | Page 17 of 20
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master will read
from the slave device. On the other hand, if the R/W bit is
low, the master will write to the slave device.
2. A write operation contains an extra instruction byte that a
read operation does not contain. Such an instruction byte
in write mode follows the slave address byte. The first bit
(MSB) of the instruction byte is a don’t care.
The second MSB, RS, is the midscale reset. A logic high on
this bit moves the wiper to the center tap where RWA = RWB.
This feature effectively writes over the contents of the
register, and thus, when taken out of reset mode, the
RDAC will remain at midscale.
The third MSB, SD, is a shutdown bit. A logic high causes
an open circuit at terminal A while shorting the wiper to
terminal B. This operation yields almost 0 in rheostat
mode or 0 V in potentiometer mode. It is important to
note that the shutdown operation does not disturb the
contents of the register. When brought out of shutdown,
the previous setting will be applied to the RDAC. Also,
during shutdown, new settings can be programmed. When
the part is returned from shutdown, the corresponding VR
setting will be applied to the RDAC.
The remainder of the bits in the instruction byte are don’t
cares (see Table 7).
3. After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Table 7).
4. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, where there
are eight data bits followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see Figure 41).
5. When all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition (see Figure 40). In read mode, the master will
issue a No Acknowledge for the ninth clock pulse (i.e., the
SDA line remains high). The master will then bring the
SDA line low before the tenth clock pulse which goes high
to establish a STOP condition (see Figure 41).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the write cycle, each data byte will
update the RDAC output. For example, after the RDAC has
acknowledged its slave address and instruction bytes, the RDAC
output will update after these two bytes. If another byte is written to
the RDAC while it is still addressed to a specific slave device
with the same instruction, this byte will update the output of
the selected slave device. If different instructions are needed, the
write mode has to start again with a new slave address, instruction,
and data byte. Similarly, a repeated read function of the RDAC
is also allowed.
Readback RDAC Value
The AD5161 allows the user to read back the RDAC values in the
read mode. Refer to Table 7 and Table 8 for the programming format.
Multiple Devices on One Bus
Figure 44 shows two AD5161 devices on the same serial bus.
Each has a different slave address since the states of their AD0
pins are different. This allows each RDAC within each device to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully I2C
compatible interface.
MASTER
AD5161
SDA SCL
RP
+5V
SDA
SCL
SDA SCL
AD5161
AD0
Figure 44. Multiple AD5161 Devices on One I2C Bus
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