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參數(shù)資料
| 型號： | EVAL-AD5232SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5232 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5232 |
| 主要屬性： | 2 通道，256 位置 |
| 次要屬性： | SPI 接口 |
| 已供物品： | 板，CD |
Data Sheet
AD5232
Rev. C | Page 21 of 24
Table 16 illustrates using the left shift-by-one to change circuit
gain in 6 dB steps.
Table 16.
SDI
SDO
Action
0xC1XX
0xXXXX
Moves Wiper W2 to double the present
data value contained in the RDAC2 register
in the direction of Terminal A.
0xC1XX
0xXXXX
Moves Wiper W2 to double the present
data value contained in the RDAC2 register
in the direction of Terminal A.
Table 17 illustrates storing additional data in nonvolatile memory.
Table 17.
SDI
SDO
Action
0x3280
0xXXXX
Stores 0x80 data in spare EEMEM location,
USER1.
0x3340
0xXXXX
Stores 0x40 data in spare EEMEM location,
USER2.
Table 18 illustrates reading back data from various memory
locations.
Table 18.
SDI
SDO
Action
0x94XX
0xXXXX
Prepares data read from USER3 location.
(USER3 is already loaded with 0x80.)
0x00XX
0xXX80
Instruction 0 (NOP) sends 16-bit word out
of SDO where the last eight bits contain
the contents of USER3 location. The NOP
command ensures that the device returns
to the idle power dissipation state.
EQUIPMENT CUSTOMER START-UP SEQUENCE
FOR A PCB CALIBRATED UNIT WITH PROTECTED
SETTINGS
1.
For the PCB setting, tie WP to GND to prevent changes in
the PCB wiper set position.
2.
Set power VDD and VSS with respect to GND.
3.
As an optional step, strobe the PR pin to ensure full power-
on preset of the wiper register with EEMEM contents in
unpredictable supply sequencing environments.
FLASH/EEMEM RELIABILITY
The Flash/EE memory array on the AD5232 is fully qualified
for two key Flash/EE memory characteristics: namely, Flash/EE
memory cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four independent,
sequential events. These events are defined as follows:
1.
Initial page erase sequence
2.
Read/verify sequence
3.
Byte program sequence
4.
Second read/verify sequence
During reliability qualification, Flash/EE memory is cycled
from 0x00 to 0xFF until a first fail is recorded, signifying the
endurance limit of the on-chip Flash/EE memory.
As indicated in the Specifications section, the AD5232 Flash/EE
memory endurance qualification has been carried out in accor-
dance with JEDEC Std. 22, Method A117 over the industrial
temperature range of 40°C to +85°C. The results allow the
specification of a minimum endurance figure over supply and
temperature of 100,000 cycles, with an endurance figure of
700,000 cycles being typical of operation at 25°C.
Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. Again, the AD5232 has been
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature of
TJ = 55°C. As part of this qualification procedure, the Flash/EE
memory is cycled to its specified endurance limit, as described
previously, before data retention is characterized. This means
that the Flash/EE memory is guaranteed to retain its data for
its full specified retention lifetime every time the Flash/EE
memory is repro-grammed. It should also be noted that
retention lifetime, based on an activation energy of 0.6 eV,
300
250
200
150
100
50
0
40
50
60
70
80
90
100
110
TJ JUNCTION TEMPERATURE (°C)
RE
T
E
N
T
IO
N
(
Y
ear
s)
02
61
8-
0
44
ADI TYPICAL PERFORMANCE
AT TJ = 55°C
Figure 44. Flash/EE Memory Data Retention
EVALUATION BOARD
Analog Devices, Inc., offers a user-friendly EVAL-AD5232-SDZ
evaluation kit that can be controlled by a personal computer
through a printer port. The driving program is self-contained;
no programming languages or skills are needed.
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